CAM Multi-Level Drive Using DACs to Cut Cell Array Area
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Solution Overview
Problem
Conventional CAM cell designs require a dramatic increase in cell area for multi-bit value storage due to the need for 2n CAM cells, which is inefficient and costly.
Innovation Solution
A CAM circuit with integrated digital-to-analog converters in word and bit line drivers to enable multi-level computation using n CAM cells, reducing the cell area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional unary encoding approach is used to store multi-bit values in CAM cells, then the CAM cells can perform Boolean operations, but the cell area increases dramatically to 2n CAM cells for an n-bit value
Solution Approach 1:
The patent changes the operating parameters of CAM cells from binary (0/1) to multi-level voltage states (e.g., 0V, 0.7V, 1.4V, 2.1V representing 0-3). This allows each CAM cell to store and process multi-bit values directly without requiring multiple cells, thereby reducing the cell array area from 2n to n cells while maintaining multi-bit computation capability
Solution Approach 2:
The patent makes each CAM cell multi-functional by enabling it to handle multiple bit values simultaneously through multi-level encoding. The same CAM cell infrastructure that performs Boolean operations is extended to also perform multi-level comparisons and arithmetic operations, eliminating the need for separate hardware structures for different operations
2Quantity of substance
If 2n CAM cells are used to store an n-bit value, then multi-bit values can be stored, but the chip area and cost increase significantly
Solution Approach 1:
The patent applies multi-level voltage encoding where each CAM cell can represent multiple bit values through different voltage levels. This parameter change allows n CAM cells to store n-bit values directly, reducing the required chip area from 2n cells to n cells while maintaining the storage capacity for multi-bit values
3Adaptability or versatility
If conventional CAM cell wiring is used for multi-bit operations, then Boolean operations are supported, but the cell area must be doubled to 2n cells
Solution Approach 1:
The patent extends the conventional Boolean operation capability of CAM cells to include multi-level operations using the same cell structure and wiring. By implementing multi-level voltage states and corresponding comparison logic, the same CAM cell infrastructure performs both traditional Boolean operations and multi-bit value operations, achieving universality without area increase
Data Source
AI summary
A content addressable memory (CAM) circuit includes a word line driver that incorporates a digital-to-analog converters (DAC), which enables the CAM circuit to store an n-bit value only with n CAM cells. The CAM circuit includes one or more of CAM cells configured to store bit values, at least one word line driver coupled to word lines of the CAM cells and configured to supply word line output to drive the CAM cells, and at least one bit line driver coupled to bit lines of the CAM cells and configured to supply bit line outputs to drive the CAM cells. The word line driver and the bit line driver include DAC circuits that includes PFETs and NFETs.