Dynamic Voltage Control for SRAM Write Assist
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Solution Overview
Problem
As SRAM cell sizes decrease, processing variations lead to device mismatches, causing write failures, and existing write assist techniques that lower supply voltage improve writeability but reduce write speed due to current fighting between pull-up and pull-down elements.
Innovation Solution
A cell voltage generator with a control unit providing variable valued pull-up enable signals to selectively connect or disconnect the supply voltage line from the cell voltage source, reducing current fighting and increasing the slew rate of the cell voltage header.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If supply voltage is lowered to improve writeability, then write failures are reduced, but write speed decreases due to current fighting between pull-up and pull-down elements
Solution Approach 1:
The patent applies dynamics by making the supply voltage time-dependent rather than static. The voltage is dynamically adjusted during the write operation: initially lowered to assist with writeability, then quickly restored to normal levels. This temporal variation in voltage resolves the contradiction by providing low voltage only when needed for overcoming device mismatches, rather than maintaining it throughout the operation which would slow down the write process.
Solution Approach 2:
The patent uses preliminary action by pre-lowering the supply voltage before the actual data flipping occurs, then quickly restoring it. The voltage reduction is applied in advance to ensure writeability is improved during the critical write operation, and then immediately reverted to prevent negative impact on write speed. This preliminary and temporary voltage adjustment resolves the trade-off between writeability and speed.
2Quantity of substance
If SRAM cell size is decreased to increase density, then storage capacity improves, but device mismatches increase causing write failures
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the supply voltage parameter during write operations. As SRAM cells are scaled down increasing density, processing variations cause device mismatches. The solution changes the voltage parameter temporarily during writes - lowering it to compensate for the increased sensitivity to mismatches in smaller cells, then restoring it afterward. This parameter adjustment resolves the contradiction between achieving high density through cell scaling and maintaining writeability despite increased device variations.
Data Source
AI summary
Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells. The cell voltage generator has a pull-down element coupled between a control node of the supply voltage line and a ground terminal, and a one or more pull-up elements connected in parallel between the control node and a cell voltage source. A control unit is configured to provide one or more variable valued pull-up enable signals to input nodes of the pull-up elements. The variable valued pull-up enable signals operate the pull-up elements to selectively connect the supply voltage line from the cell voltage source to provide a cell voltage header with a high slew rate.