3D Memory Cell Layout to Reduce Selection Transistor Etch Loading
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Solution Overview
Problem
The production yield of selection transistors in three-dimensional memory structures is susceptible to etching loading effects, leading to memory failures.
Innovation Solution
A memory structure is designed with a common bit line coupled to selection transistors through connection cells, where cells are arranged in a specific sequence to minimize etching loading effects, including interconnected first electrode dummy structures and a staircase structure for the common bit line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the selection transistor is disposed between the bit line and the common bit line in a three-dimensional memory structure, then the memory can achieve three-dimensional spatial arrangement and miniaturization, but the production yield of the selection transistor is susceptible to etching loading effects which can lead to memory failure
Solution Approach 1:
The cell array is divided into multiple regions with different cell types (storage cells, selection cells, and connection cells) arranged in a specific spatial sequence. This segmentation allows the etching process to be optimized for different regions, reducing the etching loading effect on selection transistors while maintaining three-dimensional miniaturization.
Solution Approach 2:
Connection cells are introduced as intermediary elements between the bit line and the common bit line, replacing the direct placement of selection transistors. This intermediary structure reduces the etching loading effect by distributing the etching load across multiple cells, thereby improving the production yield of selection transistors while maintaining the three-dimensional memory architecture.
2Manufacturing precision
If cells are arranged in a specific sequence including connection cells and selection cells, then the etching loading effect can be reduced, but the device structure becomes more complex
Solution Approach 1:
The cell array structure is designed to be universal, with each cell type (storage cells, selection cells, connection cells) serving multiple functions. The connection cells not only provide electrical connection but also help in reducing etching loading effects. This multi-functionality reduces the need for separate dedicated structures, thereby managing complexity while improving production yield.
Solution Approach 2:
Multiple functions are merged into the cell array structure. The selection transistors, connection cells, and bit line routing are integrated into a unified three-dimensional structure. This merging reduces the overall device complexity by eliminating the need for separate components and simplifying the manufacturing process, while still achieving reduced etching loading effects.
3Shape
If the bit line and common bit line extend in different directions parallel to the substrate, then three-dimensional spatial arrangement is achieved, but the selection transistor is more susceptible to etching loading effects
Solution Approach 1:
The memory structure transitions from a planar two-dimensional arrangement to a three-dimensional configuration. Bit lines and common bit lines extend in different directions parallel to the substrate, utilizing the third dimension (vertical stacking) to achieve spatial arrangement. This dimensional change allows selection transistors to be positioned in a manner that reduces etching loading effects while maintaining the three-dimensional architecture.
Solution Approach 2:
Different regions of the cell array are assigned different local qualities and functions. Storage cells, selection cells, and connection cells are distributed in specific spatial patterns, with each region optimized for its particular function. This local quality differentiation allows the etching process to be more effective in regions with selection transistors, improving production yield while maintaining the overall three-dimensional spatial arrangement.
Data Source
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AI summary
The present disclosure relates to a memory and a manufacturing method thereof, and an electronic device. The memory includes a common bit line, a bit line, and a cell array. The common bit line extends in a first direction parallel to a substrate. The bit line is located on a first side of the common bit line and extends in a second direction parallel to the substrate. The cell array includes a plurality of cells corresponding to the bit line, and the plurality of cells are located on a same side of the bit line and arranged in sequence in the second direction. The plurality of cells include at least one connection cell, at least one selection cell on a side of the at least one connection cell that is away from the common bit line, and a plurality of storage cells on a side of the at least one selection cell that is away from the common bit line. The storage cell and the selection cell each include a transistor coupled to the bit line. The transistor included in the selection cell is a selection transistor, and the selection transistor is coupled to the common bit line through the connection cell.