Multi-Memory Clock Synchronization Using Timing Check Circuits
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Solution Overview
Problem
Existing memory systems face challenges in synchronizing the operation of multiple memories, leading to potential operation failures.
Innovation Solution
A memory system design that includes synchronization check circuits, delay circuits, and timing check circuits to ensure that signals are received and transmitted between memories in synchronization with a clock, using differential signaling and exclusive OR gates to verify timing alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple memories operate independently without synchronization mechanism, then device complexity is reduced, but operation reliability deteriorates due to timing conflicts
Solution Approach 1:
The patent implements a feedback mechanism where each memory device transmits its received signal timing information back to the controller. The controller uses this feedback to adjust clock signals and control signals to ensure all memories operate at the same timing, thereby resolving timing conflicts and improving reliability without excessive complexity
Solution Approach 2:
The patent performs preliminary synchronization training before normal operation begins. The controller transmits training signals to multiple memory devices, and each memory responds with timing information. The controller uses this preliminary data to establish synchronized operation parameters before actual data processing starts, preventing timing conflicts in advance
2Measurement precision
If signals are transmitted without timing verification, then device complexity is reduced, but measurement precision of timing alignment deteriorates
Solution Approach 1:
The patent replaces complex hardware timing verification circuits with a software-based timing measurement and verification system. The controller uses software to measure signal timing, compare it with reference timing, and adjust synchronization parameters, achieving precise timing alignment measurement without requiring complex dedicated hardware circuits for each memory device
3Reliability
If multiple memories use separate clock signals, then ease of operation is improved, but reliability deteriorates due to timing desynchronization
Solution Approach 1:
The patent implements a universal clock signal distribution system where the controller generates a single master clock signal that is distributed to all memory devices. This master clock serves multiple functions: it synchronizes read operations, write operations, and internal timing across all memories. The system maintains ease of operation by providing a unified timing reference while ensuring reliable synchronization through this universal clock mechanism
Data Source
AI summary
A memory system may include a first memory configured to receive a first signal in synchronization with a clock, and a second memory configured to receive a second signal in synchronization with the clock. The first memory may transmit the received first signal to the second memory and the second memory may transmit the received second signal to the first memory.