Reference Voltage Generation Circuit for Resistive Memory
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Solution Overview
Problem
Resistive non-volatile memories face challenges in accurate data reading due to significant variation in reference voltage caused by process variations in reference bitcells, leading to reduced read accuracy.
Innovation Solution
A reference voltage is generated by averaging the voltages of reference bits programmed to logic '1' and '0', with periodic regeneration to track power supply voltage and temperature changes, using capacitors to ensure the voltage remains halfway between the two states, thereby reducing variation and improving sensing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single reference bitcell is used to generate reference voltage, then the device complexity is reduced, but the measurement precision deteriorates due to process variations causing great variation in reference voltage
Solution Approach 1:
The patent combines multiple reference bitcells (at least two, preferably more) to generate the reference voltage. Instead of using a single reference bitcell, the invention merges multiple reference bitcells in parallel, where each reference bitcell contributes to the overall reference voltage. This merging approach reduces the impact of process variations on any individual reference bitcell, thereby improving measurement precision while maintaining reasonable device complexity
Solution Approach 2:
The patent applies local quality by creating specialized reference bitcells with specific properties. Each reference bitcell is designed to store a specific logic state (first logic state or second logic state) and is optimized for reference voltage generation rather than data storage. This local optimization ensures that the reference voltage generation function is performed with high precision, addressing the measurement precision issue without unnecessarily increasing overall device complexity
2Measurement precision
If the reference voltage is generated by averaging multiple reference bitcells, then the measurement precision is improved, but the device complexity increases due to additional circuit components
Solution Approach 1:
The patent uses equipotentiality by connecting multiple reference bitcells in parallel, ensuring they all operate at the same potential level. The reference voltage is generated by connecting the output nodes of multiple reference bitcells together, creating an equipotential reference voltage that is more stable and less susceptible to process variations. This approach improves measurement precision while avoiding complex averaging circuits
Solution Approach 2:
The reference bitcells themselves perform the averaging function through their natural parallel connection. When multiple reference bitcells are connected in parallel, their combined output automatically represents an average of their individual states, eliminating the need for separate averaging circuitry. This self-service approach improves measurement precision through the inherent averaging effect while minimizing additional device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more stable and accurate reference voltage, enhancing the read accuracy of resistive non-volatile memory cells by minimizing voltage variation, even under changing conditions.
Implementation Method 1
a first capacitor having a first terminal coupled to the first bit line, and a second terminal, a second capacitor having a first terminal coupled to the second terminal of the first capacitor at a first node and a second terminal coupled to the second bit line
Data Source
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AI summary
A semiconductor device includes an array of memory cells, and a reference voltage generation circuit including a first set of reference memory cells coupled to a first bit line, a second set of reference memory cells coupled to a second bit line, a first capacitor having a first terminal coupled to the first bit line, and a second terminal, a second capacitor having a first terminal coupled to the second terminal of the first capacitor at a first node and a second terminal coupled to the second bit line, an amplifier including a first input selectively coupled to the first node and a second input coupled to an output of the amplifier that provides reference voltage used by sense amplifiers, and a third capacitor including a first terminal coupled to the output of the amplifier and a second terminal coupled to a first supply voltage.