3D FRAM Array Layout With Shared Lines to Limit Crosstalk
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Solution Overview
Problem
Existing memory technologies face challenges in achieving high storage density and preventing crosstalk between memory cells without increasing the physical size or complexity, particularly in ferroelectric random access memories (FRAMs).
Innovation Solution
A memory array design with a 1S1C structure, where each memory cell includes a selector and a capacitor, reduces the need for transistors within the cell, allowing for a three-dimensional stacking of memory cells while using a conventional process, and incorporates conductive vias and shared bit and plate lines to minimize crosstalk and simplify the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a 1T1C structure is used for memory cells, then read/write speed and cycle performance are improved, but storage density is reduced due to the need for transistors in each cell
Solution Approach 1:
The patent extracts the transistor function from individual memory cells by introducing a separate selector switch that is shared among multiple memory cells. This allows the memory cell to be simplified to a 1S1C structure (selector + capacitor), removing the need for transistors within each cell while maintaining the ability to selectively access cells through the shared selector mechanism.
Solution Approach 2:
The selector switch is designed to serve multiple memory cells simultaneously, acting as a universal access mechanism. By making the selector multi-functional and shareable across multiple cells, the patent achieves both fast access (through the selector's switching capability) and high storage density (by reducing the component count per cell).
2Reliability
If transistors are included in each memory cell, then selectivity and control are improved, but device complexity and process difficulty increase
Solution Approach 1:
The patent merges the selection function across multiple memory cells by using a single selector switch that can control access to multiple cells. This consolidation reduces the overall device complexity and simplifies the manufacturing process, as fewer transistors need to be fabricated and integrated compared to having dedicated transistors for each cell.
3Quantity of substance
If memory cells are stacked in three dimensions, then storage density is improved, but crosstalk between adjacent cells increases
Solution Approach 1:
The selector switch acts as an intermediary component that mediates the interaction between bit lines and memory cells. By controlling the selection process through the selector, the patent prevents unintended electrical coupling and crosstalk between adjacent cells during read/write operations, even when cells are stacked in three dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances storage density and reduces process complexity, improves read/write performance, and minimizes crosstalk, maintaining a compact footprint and efficient operation.
Implementation Method 1
the selector is turned on only when a piezoelectric difference between two terminals of the selector is greater than a specific value
Data Source
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AI summary
Embodiments of this application provide a memory and an electronic device, and relate to the field of semiconductor technologies, to provide a high-performance memory. The memory includes a plurality of first bit lines, at least one second bit line, a plurality of plate lines, a plurality of memory cells, and a plurality of transistors. The plurality of first bit lines all extend in a first direction. The at least one second bit line extends in a second direction. The plurality of plate lines all extend in the second direction, the memory cell includes a selector and a capacitor that are coupled in series, the plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and a row direction is parallel to the first direction. In a third direction, the plurality of first bit lines and the plurality of plate lines are located on two sides of the memory cell, each first bit line is coupled to at least two memory cells located in a same row, and each plate line is coupled to at least two memory cells located in a same column. A plurality of first electrodes of the plurality of transistors are correspondingly coupled to the plurality of first bit lines, and a plurality of second electrodes of the plurality of transistors are correspondingly coupled to the at least one second bit line.