Memory Array Access Lines Floating to Reduce Plate Cross-Coupling
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Solution Overview
Problem
Memory devices experience significant power loss and data integrity issues due to parasitic cross-coupling between unselected word lines and a common plate, leading to increased power consumption and potential data errors.
Innovation Solution
Floating unselected access lines during access operations to maintain a constant voltage differential with the plate, reducing unintended cross-coupling and minimizing power consumption and data errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If unselected word lines are maintained at a fixed voltage during access operations, then the memory array structure is simple and easy to control, but parasitic cross-coupling with the common plate causes significant power loss and data integrity issues
Solution Approach 1:
The patent applies the dynamics principle by transitioning unselected word lines from a static fixed voltage state to a dynamic floating state during access operations. This allows the voltage on unselected word lines to naturally track changes in the common plate voltage, maintaining a constant voltage differential and eliminating parasitic cross-coupling current while reducing power loss.
Solution Approach 2:
The patent changes the voltage parameter of unselected word lines from a fixed value to a floating state that dynamically adjusts based on plate voltage changes. This parameter change transforms the electrical characteristics of unselected word lines, enabling them to automatically compensate for plate voltage fluctuations and eliminate harmful cross-coupling effects.
2Reliability
If unselected access lines are kept at a constant voltage, then the control circuitry is simple, but leakage currents and parasitic signals disturb logic states on unselected memory cells
Solution Approach 1:
The patent makes the voltage on unselected access lines dynamic by allowing them to float during access operations. This dynamic behavior enables the access lines to automatically adjust their voltage to maintain a constant differential with the plate, preventing parasitic signals from disturbing memory cell logic states and improving data integrity.
Solution Approach 2:
The patent implements self-service by allowing unselected access lines to automatically track plate voltage changes through capacitive coupling without requiring active control circuitry. The floating access lines self-adjust their voltage level based on plate voltage transitions, eliminating the need for complex control mechanisms while maintaining data integrity.
3Quantity of substance
If multiple access lines share a common plate, then the memory cell density increases, but capacitive cross-coupling between access lines and the plate causes unintended signal interference
Solution Approach 1:
The patent applies dynamics by making unselected access lines float during access operations, enabling their voltage to dynamically track plate voltage changes. This dynamic adjustment maintains a constant voltage differential between the access lines and plate, eliminating capacitive cross-coupling and signal interference while preserving high memory cell density achieved through shared plate architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces power consumption and enhances data reliability by mitigating parasitic signals and leakage currents, improving overall performance of memory arrays.
Implementation Method 1
Memory devices experience significant power loss and data integrity issues due to parasitic cross-coupling between unselected word lines and a common plate
Data Source
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AI summary
Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.