Semiconductor Training Device for Multi-Chip Data Synchronization
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Solution Overview
Problem
Semiconductor devices with multiple chips experience delays in data input/output operations due to differences in processing times, leading to potential errors during communication with external devices.
Innovation Solution
A training device within each chip includes a pattern generation circuit, delay calculation circuit, and delay adjusting circuit to generate and compare pattern signals, calculate delay amounts, and adjust DQ signal delays to synchronize data output across chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are used to increase data capacity, then the data processing capacity is improved, but delay differences between chips cause data errors
Solution Approach 1:
The patent changes the delay parameter of each chip by inserting a configurable delay circuit that can adjust the delay time of data signals. The delay amount is determined based on the actual delay difference measured during training, allowing each chip to compensate for its inherent delay variations and achieve synchronized data output across all chips.
2Reliability
If delay adjustment circuits are added to each chip, then data synchronization is improved, but device complexity increases
Solution Approach 1:
The patent performs delay measurement and adjustment in advance during a training phase before normal operation. The delay amount for each chip is measured and stored in a register, and the delay circuit is configured with this pre-calculated value. This preliminary action eliminates the need for complex real-time delay adjustment mechanisms during data transmission.
Solution Approach 2:
Each chip independently measures its own delay characteristics and configures its own delay circuit based on the measured value. The training device generates training data and coordinates the self-test and self-adjustment process for each chip without requiring external intervention, making the system self-configuring and reducing overall complexity.
3Manufacturing precision
If delay measurement and adjustment is performed for each chip, then data output synchronization is improved, but training time and complexity increase
Solution Approach 1:
The delay adjustment is performed periodically during the training phase, which is executed once or occasionally rather than continuously. The training device initiates a training sequence that measures delays and configures the delay circuits, after which normal high-speed data transmission proceeds without repeated adjustments, minimizing the time impact.
Solution Approach 2:
The training process uses a simplified approach by skipping detailed iterative optimization and directly using the measured delay values to configure the delay circuits. The method rushes through the essential adjustment steps without unnecessary iterations, achieving sufficient synchronization precision efficiently.
Data Source
AI summary
A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a DQ signal in a chip including the corresponding training device, based on the delay amount.