HBM Data Strobe Skew Calibration Across Stacked Memory Dies
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Solution Overview
Problem
In high-bandwidth memory devices with three-dimensionally stacked memory cores, maintaining a specified phase difference of data strobe signals is challenging, leading to potential data collisions due to phase differences exceeding a specified threshold, which affects data transmission efficiency.
Innovation Solution
A memory device with a buffer die that includes a DQS generation circuit, a DQS calibration circuit, and a coefficient decision circuit to generate and compensate for skew in data strobe signals by detecting latency and applying weighted calibration codes to synchronize data transmission across core dies through TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensionally stacked memory cores are used to increase memory bandwidth, then integration and bandwidth are significantly improved, but phase difference of data strobe signals cannot be maintained and data collision errors occur
Solution Approach 1:
The patent applies preliminary action by performing skew calibration before normal data transmission. The calibration process measures phase differences and generates calibration codes in advance, which are then stored and applied during operation to maintain correct timing relationships between data strobe signals from multiple core dies.
Solution Approach 2:
The patent implements feedback through a calibration loop that measures actual phase differences between data strobe signals, compares them against target values, and adjusts timing accordingly. The DQS calibration circuit continuously monitors and corrects skew conditions, creating a closed-loop system that maintains signal integrity.
2Device complexity
If data strobe signals are transmitted through TSVs to core dies, then integration is improved, but specified phase difference cannot be maintained leading to data collisions
Solution Approach 1:
The patent changes the timing parameter of data strobe signals through skew calibration. By measuring actual phase differences and applying calibration codes that adjust signal timing, the system compensates for manufacturing variations and maintains the specified phase difference even though signals travel through TSVs with different path lengths.
3Reliability
If skew calibration is performed for each rank signal, then data collision errors are reduced, but device complexity increases
Solution Approach 1:
The patent segments the calibration process by handling each rank signal independently. The DQS calibration circuit measures and calibrates each data strobe signal separately, generating individual calibration codes for each rank. This modular approach allows systematic compensation of phase differences without requiring complex centralized control.
Data Source
AI summary
A memory device includes core dies including memory cell arrays, and a buffer die electrically connected to the core dies through one or more through silicon vias. The buffer die includes a DQS generation circuit that receives an external clock signal from an external device and generates data strobe signals based on the external clock signal for communicating data with the core dies, a DQS calibration circuit that detects a latency of each of plural rank signal that are received from the core dies based on the data strobe signals, respectively, and a coefficient decision circuit that detects a threshold voltage code of the buffer die, applies a weight to the latency of each rank signal based on the threshold voltage code to generate a weighted calibration code for each rank signal, and transmits the weighted calibration codes to respective ones of the core dies.