RRAM Local Interconnect Layout Without Extra Planarization
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Solution Overview
Problem
The integration of resistive random access memory (RRAM) in the via of local interconnection in the back-end process causes top surface unevenness, necessitating an additional planarization process to maintain the original design position.
Innovation Solution
The RRAM structure is arranged in the first metal layer of the local interconnection without requiring an additional planarization process by integrating it with the first metal layer process, ensuring the top surface alignment with the metal interlayer dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RRAM is inserted in the via of local interconnection in the back-end process, then non-volatile memory functionality is achieved, but top surface unevenness occurs requiring additional planarization process
Solution Approach 1:
The patent merges the RRAM structure with the first metal layer of the local interconnection, integrating memory functionality into the existing interconnection architecture. This combination eliminates the need for separate via insertion and additional planarization processes, as the RRAM is formed within the metal layer structure itself during the back-end process
Solution Approach 2:
The patent transitions from inserting RRAM vertically in a via to forming RRAM within the horizontal plane of the first metal layer. This dimensional change allows the memory structure to be integrated into the interconnection layer rather than disrupting the via structure, thereby maintaining surface planarity without additional processing
2Reliability
If RRAM is inserted in the via of local interconnection, then memory cell functionality is achieved, but top surface position shifts from original design
Solution Approach 1:
By merging the RRAM structure with the first metal layer, the patent ensures that the memory structure follows the original designed horizontal position of the local interconnection. The RRAM is formed within the metal layer boundaries, maintaining alignment with the original design without requiring additional planarization to correct position shifts
3Manufacturing precision
If additional planarization process is used to smooth top surface, then horizontal position alignment is maintained, but manufacturing efficiency decreases
Solution Approach 1:
The patent extracts the planarization step from the manufacturing process by designing the RRAM structure to inherently maintain surface planarity. The RRAM is formed within the first metal layer in such a way that no additional planarization process is required, thereby removing this step from the manufacturing sequence and improving overall productivity while maintaining horizontal position alignment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains the original horizontal position of the local interconnection, eliminating the need for additional planarization and enhancing manufacturing efficiency.
Implementation Method 1
The main operating principle of RRAM is to change the resistance of the metal oxide by applying bias voltage so as to store data
Data Source
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AI summary
A resistive random access memory structure, comprising: a substrate; a transistor disposed on the substrate, wherein the transistor comprises a gate structure, a source and a drain; a single drain contact plug having an end contacting the drain; a metal interlayer dielectric layer disposed on the drain contact plug; a resistive random access memory, RRAM, disposed on the drain and within a first trench in the metal interlayer dielectric layer, wherein the RRAM comprises the drain contact plug, a metal oxide layer and a top electrode, the drain contact plug serves as a bottom electrode of the RRAM, the metal oxide layer directly contacts another end of the single drain contact plug and the top electrode contacts the metal oxide layer; and a metal layer disposed within the first trench; the resistive random access memory structure further comprising: a second trench disposed within the metal interlayer dielectric layer, a source contact plug contacting the source and being exposed from the second trench, a buffer layer and the metal layer disposed within the second trench, and the buffer layer contacting the source contact plug.