Configurable Memory Metadata for Shared System and Link ECC
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Solution Overview
Problem
Existing error correction schemes in computing devices are inefficient and costly, particularly due to the use of high-density on-chip SRAM for system-level ECC, which is expensive and susceptible to soft errors, while separate memory link ECCs add complexity and cost.
Innovation Solution
Implementing a system ECC function that shares resources with link ECC, utilizing signal connections to generate and transfer parity bits within the host and memory device, reducing the need for on-chip SRAM and enhancing data reliability without additional memory links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-density on-chip SRAM is used for system-level ECC, then data reliability is improved, but system cost increases and susceptibility to soft errors worsens
Solution Approach 1:
The patent merges system ECC and link ECC into a unified multi-layer ECC architecture. The memory device performs both system-level ECC (protecting data in the memory array) and link-level ECC (protecting data during transmission) using shared hardware resources, eliminating the need for separate high-density SRAM blocks for each ECC type. This integration reduces overall system cost while maintaining comprehensive data protection.
Solution Approach 2:
The memory device is designed with multi-functional ECC capabilities that can operate in different modes. The same ECC hardware can function as system ECC when data is stored in the memory array and as link ECC when data is transmitted via data connections. This universal approach replaces the need for dedicated high-density SRAM for system ECC, reducing cost and soft error susceptibility.
2Reliability
If separate memory link ECCs are implemented, then data reliability during transmission is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines system ECC and link ECC functions into a single integrated ECC engine within the memory device. This unified architecture performs both system-level error correction (for data stored in the memory array) and link-level error correction (for data transmitted over data connections) using shared hardware resources, thereby reducing device complexity and cost while maintaining transmission reliability.
Solution Approach 2:
The ECC hardware is designed with universal functionality to operate in multiple modes. The same ECC circuitry can protect data in the memory array (system ECC mode) and protect data during transmission (link ECC mode), eliminating the need for separate dedicated ECC hardware for each function and reducing overall device complexity.
3Reliability
If on-chip SRAM is used for ECC storage, then error correction capability is improved, but susceptibility to soft errors worsens
Solution Approach 1:
The patent replaces expensive and vulnerable high-density on-chip SRAM with alternative storage mechanisms that are more resistant to soft errors. The ECC data can be stored in more robust memory structures or regenerated on-demand using the unified ECC engine, eliminating the single point of failure that high-density SRAM represents in harsh environments.
Solution Approach 2:
By merging system ECC and link ECC into a unified architecture, the patent reduces the total amount of ECC storage required. The shared ECC engine can serve both functions, reducing the dependency on large blocks of on-chip SRAM and thereby reducing exposure to soft errors while maintaining comprehensive error correction capability.
Data Source
AI summary
Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.