Memory Buffer Reference Clock Selection Logic
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Solution Overview
Problem
Double-data rate (DDR) memory systems face issues with clock jitter and long-term drift due to the relatively slow frequency of the system reference clock, which affects the alignment of command slots and internal clock generation in memory buffers.
Innovation Solution
Implementing reference clock selection logic to selectively set a memory command clock as the reference clock, allowing for the use of a higher frequency memory command clock to reduce jitter and drift, which includes integrating or separating the logic within the memory buffer and using a phase-locked loop to lock the memory command clock for generating internal clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a system reference clock from a common clock source is used, then the system operates with a stable reference clock, but the frequency is relatively slow causing clock jitter and long-term drift
Solution Approach 1:
The patent implements dynamic reference clock selection that allows the system to switch between system reference clock and memory command clock based on operational requirements. The memory buffer can dynamically select which clock source to use, enabling adaptation between stability-oriented and speed-oriented modes of operation.
Solution Approach 2:
The patent changes the reference clock frequency parameter by allowing selection between two different clock sources: the system reference clock (lower frequency, higher stability) and the memory command clock (higher frequency). This parameter change resolves the contradiction by providing both low-frequency stability and high-frequency operation at different times.
2Reliability
If a higher frequency memory command clock is used as reference clock, then clock jitter and long-term drift are reduced, but additional clock selection logic and phase-locked loop circuitry are required
Solution Approach 1:
The memory buffer is designed with multi-functionality to handle both system reference clock and memory command clock inputs. The same memory buffer structure processes commands from either clock source, eliminating the need for separate processing paths and reducing overall system complexity despite adding clock selection capabilities.
Solution Approach 2:
The patent introduces a phase-locked loop (PLL) as an intermediary component that conditions the memory command clock before it is used as a reference clock. The PLL ensures proper phase alignment and frequency stabilization, making the higher frequency clock suitable for reference purposes while managing the complexity through a dedicated intermediary circuit.
3Stability of the object's composition
If the system reference clock is used for generating internal clocks, then the system maintains consistent timing, but the alignment of command slots targeting specific memory channels deteriorates due to jitter and drift
Solution Approach 1:
The patent performs preliminary action by training the memory link using the memory command clock before normal operation begins. This training process establishes optimal command slot alignment and timing relationships while the high-frequency clock is available, preparing the system for precise operation before potential switching to the system reference clock occurs.
Solution Approach 2:
The system dynamically adjusts its reference clock source based on operational phase and performance requirements. During training and high-precision operations, the memory command clock is used to ensure accurate command slot alignment. During normal steady-state operation, the system can switch to the system reference clock for timing consistency, with the capability to switch back if alignment precision deteriorates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces clock jitter and long-term drift, improving the alignment and stability of internal clocks within memory buffers, enhancing the performance of DDR memory systems.
Implementation Method 1
using a phase-locked loop to lock the memory command clock for generating internal clocks
Data Source
AI summary
Described herein are embodiments of selectively setting a memory command clock as a memory buffer reference clock. An apparatus configured for setting a memory command clock as a memory buffer reference clock may include a memory buffer configured to interface between a host and memory, and reference clock selection logic configured to selectively set a memory command clock as a memory buffer reference clock. Other embodiments may be described and/or claimed.