Semiconductor Memory Sub-bit Line Segmentation
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Solution Overview
Problem
In magnetoresistive random access memory (MRAM) systems, the miniaturization of memory cells leads to insufficient cutoff resistance properties of MIS transistors, resulting in leak currents that degrade the read margin due to the fluctuation of bit line potentials caused by non-selected cells.
Innovation Solution
The semiconductor memory design incorporates a configuration where each memory cell is connected to a main bit line and a sub-bit line, with the sub-bit lines of non-selected cells set to the same potential as the main bit line, reducing the cutoff current and maintaining the read margin by minimizing potential differences across bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If memory cells are miniaturized to increase storage capacity, then cell size is reduced, but cutoff resistance properties of MIS transistors become insufficient and cutoff current increases
Solution Approach 1:
The bit line is divided into a main bit line and a sub-bit line, creating separate current paths. The select transistor's source/drain is connected to the sub-bit line rather than directly to the main bit line, segmenting the current flow to reduce cutoff current impact on the main bit line potential
Solution Approach 2:
The sub-bit line acts as an intermediary between the select transistor and the main bit line. By routing the transistor's cutoff current through the sub-bit line instead of directly into the main bit line, the sub-bit line serves as a mediator that isolates the harmful cutoff current from affecting the read operation on the main bit line
2Area of moving object
If memory cells are miniaturized to increase storage capacity, then cell size is reduced, but read margin degrades due to bit line potential fluctuation from cutoff current
Solution Approach 1:
Dividing the bit line into main and sub-bit lines separates the read current path (main bit line) from the cutoff current path (sub-bit line), preventing cutoff current from causing potential fluctuations on the main bit line that would degrade read margin
Solution Approach 2:
The sub-bit line serves as an intermediary that captures and channels the cutoff current away from the main bit line, protecting the main bit line's potential stability and thus preserving read margin
3Reliability
If select transistor size is increased to improve cutoff resistance, then transistor dimensions are enlarged, but memory cell area increases reducing storage capacity
Solution Approach 1:
By segmenting the bit line connection so that the select transistor connects to the sub-bit line rather than the main bit line, the transistor can be made smaller without compromising the main bit line's cutoff resistance performance, as the sub-bit line isolates the transistor's cutoff current
Data Source
AI summary
A semiconductor memory of an aspect of the present invention including a main bit line, a first and second sub-bit line, a first resistive memory element which has a first terminal being connected with the main bit line, a first select transistor which has one end of a first current path being connected with the second terminal of the first resistive memory element and the other end of the first current path being connected with the first sub-bit line, a second resistive memory element which has a third terminal being connected with the main bit line, and a second select transistor which has one end of a second current path being connected with the fourth terminal of the second resistive memory element and the other end of the second current path being connected with the second sub-bit line.