Shared Phase Decoder Layout for Compact DRAM Memory Arrays
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Solution Overview
Problem
Current DRAM memories face challenges with large size and high power consumption due to the area occupied by row decoders and the need for numerous phase decoder circuits, which also complicate wiring and increase power consumption.
Innovation Solution
Implementing a shared phase decoder system where different memory sections share the same phase decoder, reducing the area and power consumption by optimizing wiring and signal timing, and balancing driving effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate phase decoders are used for each memory section, then signal timing and driving capability are sufficient, but the row decoder area and power consumption increase significantly
Solution Approach 1:
Multiple memory sections share a common phase decoder instead of each having a separate decoder. The phase decoder outputs are distributed to multiple memory sections through shared wiring, reducing the total number of decoder circuits and their associated area while maintaining proper signal distribution to all sections.
Solution Approach 2:
The phase decoder is designed to serve multiple memory sections simultaneously. A single phase decoder circuit performs the function of generating phase signals for multiple different memory sections, making the decoder multi-functional and reducing overall system complexity and area.
2Power
If separate phase decoders are used for each memory section, then driving capability is sufficient, but power consumption increases due to excessive devices
Solution Approach 1:
Multiple memory sections share a common phase decoder instead of each having a separate decoder. The phase decoder outputs are distributed to multiple memory sections through shared wiring, reducing the total number of decoder circuits and their associated area while maintaining proper signal distribution to all sections.
Solution Approach 2:
The phase decoder is designed to serve multiple memory sections simultaneously. A single phase decoder circuit performs the function of generating phase signals for multiple different memory sections, making the decoder multi-functional and reducing overall system complexity and area.
3Area of stationary object
If phase decoders are shared among memory sections, then area and power consumption are reduced, but wiring complexity increases
Solution Approach 1:
The wiring architecture is reorganized by introducing a hierarchical distribution structure. Phase decoder outputs are first distributed along bit line extensions in one dimension, then further distributed to specific memory sections. This dimensional organization of wiring reduces complexity compared to direct point-to-point connections.
Solution Approach 2:
The wiring system is segmented into hierarchical levels: first-level distribution along bit line extensions and second-level distribution to individual memory sections. This segmentation allows complex wiring to be broken down into manageable segments that can be independently routed and managed.
4Area of stationary object
If phase decoders are shared among memory sections, then area is reduced, but signal timing balance becomes challenging
Solution Approach 1:
The wiring architecture is reorganized by introducing a hierarchical distribution structure. Phase decoder outputs are first distributed along bit line extensions in one dimension, then further distributed to specific memory sections. This dimensional organization of wiring reduces complexity compared to direct point-to-point connections.
Solution Approach 2:
The wiring design ensures that signal paths to different memory sections are length-matched and impedance-matched, creating equipotential conditions for signal arrival. By equalizing the electrical characteristics of different signal paths, timing balance is achieved despite the shared decoder architecture.
Data Source
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AI summary
Embodiments of the present application relate to the field of memories and provide a memory. The memory includes a first phase decoder, a first memory section, and a second memory section. The first memory section and the second memory section are arranged in sequence in a first direction, where the first direction is an extension direction of bit lines. The first phase decoder is connected to the first memory section and outputs a plurality of first phase signals to the first memory section. The first phase decoder also outputs the plurality of first phase signals to the second memory section. In this way, at least the area of the memory can be reduced.