Sense Amplifier Offset Elimination for Stable DRAM Bit-Line Sensing
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Solution Overview
Problem
The offset voltage induced by differences in characteristics of nMOSFETs and pMOSFETs in sense amplifiers of dynamic random access memory devices leads to reduced sense margin and difficulty in accurately detecting sensed signals, exacerbated by variations in threshold voltage due to process temperature stress (PVT), making it challenging to improve sensing operations.
Innovation Solution
A semiconductor memory device with a control unit that adjusts voltages based on the characteristics of pMOSFETs and nMOSFETs to ensure bit-line voltages are close to a specific target voltage during offset elimination operations, using VGP, VBBP, VGN, and VBBN generation units to equalize effective resistances and maintain consistent bit-line voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the effective resistance of nMOSFETs is made equal to that of pMOSFETs to reduce bit-line voltages during offset elimination operation, then sensing accuracy is improved, but device complexity increases due to additional control circuits and voltage adjustment mechanisms
Solution Approach 1:
The patent adjusts the effective resistance of transistors by changing their operating parameters (gate voltages, channel widths, lengths) to equalize the effective resistance between nMOSFETs and pMOSFETs. This parameter adjustment equalizes voltage drops during offset elimination, improving sensing accuracy without requiring fundamental circuit redesign
Solution Approach 2:
The sense amplifier is divided into multiple transistor pairs with independently adjustable characteristics. By segmenting the circuit into controllable units, the patent can adjust individual transistor parameters to achieve overall resistance matching, resolving the contradiction between accuracy improvement and device complexity
2Manufacturing precision
If transistor characteristics are made uniform across all sense amplifiers to simplify control, then manufacturing precision is improved, but adaptability to PVT variations deteriorates
Solution Approach 1:
The patent implements dynamic adjustment mechanisms that allow transistor characteristics to be modified in real-time based on operating conditions. This enables the sense amplifiers to adapt to PVT variations while maintaining manufacturing simplicity, as the system can dynamically compensate for environmental changes rather than requiring precise initial uniformity
Solution Approach 2:
The patent allows transistor parameters (such as gate voltages and effective resistances) to be changed based on detected PVT conditions. This parameter adaptability enables the system to maintain performance across varying temperatures and process conditions without requiring extremely tight manufacturing tolerances
3Measurement precision
If bit-line voltages are reduced during charge sharing operation to improve signal detection, then measurement precision is improved, but the voltages generated during offset elimination operation must be precisely controlled, increasing device complexity
Solution Approach 1:
The patent employs feedback mechanisms that monitor bit-line voltages during both offset elimination and charge sharing operations. This feedback allows the control circuit to dynamically adjust transistor parameters to achieve the desired voltage levels, improving signal detection while managing control complexity through automated closed-loop control
Solution Approach 2:
The patent performs preliminary offset elimination with controlled voltages before the actual charge sharing operation. By preparing the bit-lines in advance with appropriate voltage levels and transistor states, the system simplifies the subsequent signal detection phase, as the preliminary action has already established favorable conditions for accurate measurement
Data Source
AI summary
A semiconductor memory device is provided and includes at least one sense amplifier and a control unit. The at least one sense amplifier includes a pair of first transistors and a pair of second transistors. The control unit provides voltages that are adjusted based on characteristics of the pair of first transistors and the pair of second transistors of each sense amplifier of the at least one sense amplifier to the pair of first transistors and the pair of the second transistors of each sense amplifier of the at least one sense amplifier so that voltages of a pair of bit lines connected to each sense amplifier of the at least one sense amplifier are close to a specific target voltage during an offset elimination operation.