Row Decoder Address Remapping for Damaged Memory Blocks
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Solution Overview
Problem
Conventional row/column redundancy and ECC techniques are insufficient for completely repairing damaged memory cells, leading to reduced product yield and inability to ship partially damaged memory devices as normal products.
Innovation Solution
A row decoder circuit with a pre-decoder, decoders, and a mapping control circuit that reorders row address ranges based on verification data to skip damaged memory blocks during mapping, allowing the device to function normally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional row/column redundancy and ECC techniques are used to repair damaged memory cells, then some memory cells can be repaired, but the repair capability is limited and cannot completely repair all damaged memory cells
Solution Approach 1:
The mapping control circuit performs preliminary identification of damaged memory blocks during manufacturing testing using verification data, and pre-configures the mapping relationship before the memory device is shipped. This preliminary action allows the system to proactively avoid damaged blocks rather than attempting repair after damage occurs, thereby achieving complete functionality while maintaining high product yield.
Solution Approach 2:
The patent introduces a mapping control circuit as an intermediary component between the address input and the memory array. This intermediary translates logical row addresses to physical row addresses, enabling the system to bypass damaged memory blocks through address remapping. The mapping control circuit acts as a mediator that redirects access away from damaged areas without requiring repair of the underlying memory cells.
2Productivity
If memory devices with random damage positions are shipped as normal products, then product yield is maintained, but the damaged memory cells cannot be accessed reliably
Solution Approach 1:
The mapping control circuit serves as an intermediary layer that sits between the processor and the memory array, translating logical addresses to physical addresses while bypassing damaged blocks. This intermediary enables the system to maintain high product yield by allowing damaged devices to be shipped, while simultaneously ensuring reliable memory access through dynamic address remapping that redirects all accesses away from damaged regions.
Solution Approach 2:
The system changes the mapping parameter (address translation relationship) dynamically based on the identified damage locations. By modifying how logical addresses map to physical addresses, the system can adapt to different damage patterns in each memory device, ensuring reliable access to functional memory cells while maintaining overall system operation. This parameter change allows the same hardware to reliably serve different physical layouts.
3Reliability
If all memory cells are required to be 100% damage-free, then reliability is maximized, but the damage rate of each die makes this almost impossible to achieve
Solution Approach 1:
The system performs preliminary damage identification and mapping configuration during manufacturing testing, before the memory device is shipped to customers. By identifying damaged blocks in advance and pre-configuring the mapping relationships, the system accepts that some damage exists but ensures it does not affect normal operation. This preliminary action transforms the approach from requiring 100% damage-free cells to proactively managing and bypassing damaged areas.
Solution Approach 2:
The patent converts the harmful effect of damaged memory cells into a beneficial outcome by using the mapping control circuit to identify and isolate damaged blocks, then redirecting all accesses to healthy blocks. The presence of damaged cells, which would normally reduce yield, becomes an opportunity to demonstrate the robustness of the remapping mechanism. The harm of random damage is transformed into a benefit by showing that the system can tolerate and adapt to damage while maintaining full functionality and high product yield.
Data Source
AI summary
A row decoder circuit adapted to a memory device is provided. The row decoder circuit includes a pre-decoder, multiple decoders, and a mapping control circuit. The pre-decoder is configured to receive row address information and decode the row address information to provide a row select signal group. The decoders sequentially correspond to multiple row address ranges. The mapping control circuit is configured to obtain a selected raw address range according to the row select signal group, and cause the decoder whose corresponding row address range is the same as the selected row address range to output a word line signal. The mapping control circuit reorders the row address ranges corresponding to the decoders according to verification data.