Multilevel Resistive Memory Cell Using Series Conductance States
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Solution Overview
Problem
Existing resistive memory devices are limited to two states, which restricts the bit density and efficiency of non-volatile memory circuits.
Innovation Solution
A memory cell design that couples a resistive memory device in series with a switching device, allowing for four programmable states by combining the resistive memory's resistance levels with the switching device's conductance levels, enhancing bit density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a resistive memory device is used with only two resistance states, then the device structure remains simple, but the bit density is limited
Solution Approach 1:
The patent combines a resistive memory device with a switching device in a single memory cell structure. The resistive memory device provides two resistance states (HRS and LRS) while the switching device provides two conductance states, creating four distinct programmable states total. This merging of two functional components enables increased bit density without requiring four separate memory cells per bit
Solution Approach 2:
The patent utilizes changes in electrical parameters (resistance and conductance) to encode multiple data states. By programming the resistive memory device to different resistance levels and the switching device to different conductance levels, the system achieves four distinct programmable states that can represent two bits of data, thereby increasing bit density through parameter variation rather than structural multiplication
2Quantity of substance
If only two resistance states are used in resistive memory devices, then the programming process is simple, but the memory capacity is restricted
Solution Approach 1:
The patent merges the state representation capabilities of two binary components (resistive memory device and switching device) to achieve quadruple-state memory. Each component independently contributes one bit of information, and their combination in series creates four distinguishable states, effectively doubling the memory capacity per cell while maintaining relatively simple binary programming processes for each component
Solution Approach 2:
The memory cell structure serves multiple functions: the resistive memory device provides non-volatile storage capability with two resistance states, while the switching device provides additional state differentiation through two conductance states. This multi-functional design enables the single cell to store two bits of information, achieving higher memory capacity without requiring separate storage elements for each bit
Data Source
AI summary
An IC device includes first and second terminals that receive bit and source line signals configured by a control circuit, a resistive memory device having first and second resistance levels in first and second states, and a switching device including control and body terminals and a current path. The resistive memory device and the current path are coupled in series between the first and second terminals, the current path, responsive to a first voltage level at the control terminal, has a first conductance level in a first programmed state and a second conductance level greater than the first conductance level in a second programmed state, and the control circuit sets the resistive memory device to one of the first or second resistance levels after programming the switching device to the second conductance level and while increasing the second conductance level responsive to a second voltage level at the body terminal.