3D Thin-Film Transistor Structure for Low-Resistance Memory Cells
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Solution Overview
Problem
As the size of thin film transistors (TFTs) decreases, the contact area between the source/drain and channel layer reduces, leading to increased contact resistance, affecting the on-state current and making it difficult to meet requirements for high storage density and high read speed in memories.
Innovation Solution
A thin film transistor with a three-dimensional structure is designed, featuring a vertical channel configuration and graded conductivity in the channel layer, utilizing indium gallium zinc oxide with varying metal doping to reduce contact resistance and increase on-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of TFT is continuously reduced to increase storage density, then the area occupied by each memory cell is reduced, but the contact area between source/drain and channel layer is reduced, leading to increased contact resistance and decreased on-state current
Solution Approach 1:
The patent transitions from a planar TFT structure to a vertical channel TFT structure. The channel extends in the vertical direction from the first electrode through the gate dielectric layer to the gate base, creating a three-dimensional configuration. This dimensional change allows the channel length to be defined vertically rather than laterally, enabling smaller planar footprints while maintaining adequate channel dimensions for acceptable contact resistance.
Solution Approach 2:
The patent implements a graded conductivity channel layer where the conductivity varies along the channel length. The first region (near source/drain contacts) has higher conductivity to reduce contact resistance, while the second region (near gate) has lower conductivity for proper channel control. This local variation in material properties optimizes both contact resistance and transistor performance in the miniaturized structure.
2Area of moving object
If the size of TFT is continuously reduced to increase storage density, then the area occupied by each memory cell is reduced, but the on-state current is affected due to increased contact resistance
Solution Approach 1:
The vertical channel configuration allows the channel to extend through multiple layers (first electrode, gate dielectric, gate base) in the vertical direction, maintaining sufficient channel length for current flow while minimizing the planar area occupied by the transistor. This enables high-density memory integration without sacrificing on-state current capability.
Solution Approach 2:
The graded conductivity structure creates a high-conductivity region at the source/drain contact interfaces to ensure low contact resistance and high current injection efficiency, while maintaining lower conductivity in the gate-controlled region for proper transistor operation. This local optimization ensures high on-state current in miniaturized devices.
3Area of moving object
If the contact area between source/drain and channel layer is reduced, then the device size is reduced for higher density, but the contact resistance is increased
Solution Approach 1:
The channel layer is designed with spatially varying conductivity: the first region adjacent to source/drain electrodes has higher conductivity to minimize contact resistance, while the second region adjacent to the gate has lower conductivity for effective channel control. This local property variation allows small contact areas to achieve low contact resistance through optimized material composition rather than increased area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively reduces contact resistance, increases the on-state current, and enhances the read/write speed of memory cells, allowing for higher storage density and faster operations.
Implementation Method 1
Conductivities of the channel layer are gradually decreased in a direction from the first surface to the second surface
Data Source
AI summary
Examples of a thin film transistor and a memory are described. One example thin film transistor includes a first electrode, a gate, a gate dielectric layer, a channel layer, and a second electrode. The gate includes a gate base and a gate pillar. The gate base is located on the first electrode, and the gate pillar is located between the gate base and the first electrode. The gate dielectric layer is located between the first electrode and the gate pillar. The channel layer is at least partially located between the first electrode and the gate base. The second electrode is located between the first electrode and the gate base, and is located on a side that is of the channel layer and that is away from the gate pillar. Both the second electrode and the first electrode are in contact with the channel layer.