3D CCD Word Line Contacting Scheme for High-Density Memory
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Solution Overview
Problem
The challenge lies in designing a 3D CCD memory with high memory cell density while balancing manufacturing throughput and process complexity, without significantly increasing area overhead.
Innovation Solution
A contacting scheme for a 3D multi-phase CCD memory is introduced, featuring a stack of alternating gate and spacer layers with semiconductor-based channels forming charge storage capacitors, and contact vias that connect disjoint groups of gate layers efficiently, allowing for high density and reduced area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more layers are added to the stack to increase memory cell density, then memory density is improved, but area overhead due to staircase structure increases too much
Solution Approach 1:
The patent transitions from a conventional 2D planar contact layout to a 3D vertical contact via architecture. Contact vias extend through multiple gate layers in the vertical dimension, allowing high-density memory cells to be accessed without expanding the lateral footprint. This dimensional change enables memory density improvement while controlling area overhead by utilizing the third dimension (vertical depth) for contact routing.
Solution Approach 2:
The contact vias are nested within the stack structure, passing through multiple alternating gate and spacer layers. The contact vias are positioned to align with specific gate layers while navigating through the vertical stack, effectively nesting the contact structure within the memory array footprint rather than adding external contact areas.
2Ease of operation
If a staircase-like structure is used to access gate layers, then gate layer accessibility is improved, but manufacturing complexity increases
Solution Approach 1:
The gate layers are divided into disjoint groups, with each contact via associated with one specific group. This segmentation allows independent formation and alignment of contact vias for each gate layer group, simplifying the manufacturing process compared to a continuous staircase structure. Each contact via can be formed and aligned independently, reducing process complexity while maintaining gate layer accessibility.
3Adaptability or versatility
If multiple individual gate electrodes are incorporated in a unit memory cell for multi-phase CCD memory, then charge transport capability is improved, but process complexity increases
Solution Approach 1:
The contact via structure serves multiple functions simultaneously: it provides electrical access to multiple gate layers, acts as an alignment reference for subsequent processing steps, and enables charge transport across multiple phases. This multi-functional design reduces process complexity by consolidating several requirements into a single structural element rather than requiring separate structures for each function.
Data Source
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AI summary
The present disclosure relates to a charge-coupled device (CCD) memory. In particular, the disclosure provides a design and a contacting scheme for a three-dimensional (3D) integrated CCD memory, which may be a multi-phase CCD memory. The 3D CCD memory comprises a stack including a plurality of gate layers and spacer layers, which are alternatingly arranged one on the other along a first direction; a plurality of semiconductor-based channels extending in the stack. The channels form, in combination with the gate layers and one or more gate dielectric layers, a plurality of strings of charge storage capacitors operable as a plurality of CCD registers. A plurality of contact vias extend in the stack. Each contact via is associated with one group of a plurality of disjoint groups of the gate layers, and is electrically connected to all the gate layers of the group it is associated with, wherein at least one of the groups comprises two or more gate layers.