Solid-State Devices TRIZ Cases

A staged charge pump generates high negative bias for the sensor isolation layer, reducing dark current and improving image quality.

Grouped vertical contact vias replace staircase access in 3D CCD memory, raising density while limiting area overhead and process complexity.

A ZnO thin-film insulating layer suppresses surface defects in light emitting stacks, improving efficiency, lifetime, and array insulation.

A transparent conductive capping layer shields exposed lower metal during pixel electrode etching, preserving display reliability.

Three light sources with distinct chromaticities tune melanopic ratio across color temperatures while preserving color rendering and efficiency.

A vertically stacked 2T-1C cell places the capacitor between transistors to preserve capacitance and increase DRAM array density.

Segmented shallow and deep trench formation with dielectric liners simplifies varying-depth IC isolation and reduces defect-prone processing.

Carrier injection from doped junctions forms an inversion layer that improves erase/program efficiency, widens memory window, and lowers gate breakdown risk.

An isolation structure separates anodes from the planarization layer, preserving display quality while enabling light transmission for under-screen cameras.

Blocking and support portions in a deposition mask prevent external shadows, reduce bezel size, and spread pressure on display substrates.

A mask-reducing electrode layout aligns light emitting elements more precisely, simplifying fabrication and improving light emission efficiency.

Controlled bank thickness and sidewall angle disperse condensation stress, preventing cracks in the organic insulating layer.

A fixed-potential shielding layer lets LEDs overlap the drive circuit, expanding display area while limiting noise in narrow-bezel panels.

MIS field modulation and isolated contacts help vertical micro-LED arrays cut leakage, charge crowding, and non-radiative recombination.

A larger red micro-LED area balances RGB luminance while sub-100 μm units help limit sidewall non-radiative recombination losses.

Isolation structures and reflective layers separate mixed pixel types to curb optical crosstalk and preserve low-light sensitivity.

Specific host energy alignment improves exciton transfer and cuts charge trapping, keeping OLED driving voltage low while extending lifespan.

Alternating data and dummy pads enable straight die-to-die connections, cutting parasitic capacitance and stack complexity.

Mounting LED chips at different angles improves far-field light overlap, reducing viewing-angle color shift and uneven distribution.

Staggered openings in first and second insulating layers relieve bending stress in curved displays while preserving layer thickness and reliability.

Embedding multiple electrodes within a capacitor structure boosts capacitance for signal filtering while fitting standard logic IC manufacturing flows.

A recessed semiconductor contact lets the common electrode directly reach the second semiconductor layer, cutting resistance and display power loss.

A black optical layer and planarized packaging structure suppress silver-gray off-state appearance, improve flatness, and protect LED chips.

Spacer pillars formed with color filter layers simplify LCD panel manufacturing while maintaining cell-gap support, elasticity, and substrate alignment.

An undercut planarization structure separates reflective and auxiliary electrode regions in one process, improving light output and color purity.

A bottom dielectric isolator blocks leakage between stacked CFET source/drain epitaxy and the gate while preserving high device density.

An external resistor on the SCR tap region lowers capacitance, reducing I/O impact while preserving ESD protection in integrated circuits.

A two-layer recess structure traps metal debris from outer lead burrs, preventing short-circuits and defects during semiconductor transport.

Parallel bank access across stacked memory die aggregates bandwidth through one data interface while limiting through-die via area overhead.

An insulating pattern between the memory layer and source structure preserves electrical characteristics and yield in high-density semiconductor stacks.

An extended alignment layer lets binding terminals sit closer to the active area, shrinking display bezels without losing stable chip conduction.

A reflective structure around a vertical LED redirects divergent light toward the normal direction to raise display panel brightness.

Using polycrystalline TFTs for driving and oxide TFTs for pixels cuts power use, supports VRR, and keeps fabrication simpler.

A symmetric magnetic-layer LED structure improves self-assembly accuracy and bonding while preserving emission area and light extraction.

Clean supply and ground protection paths discharge trapped DNW charge to prevent gate oxide damage and popcorn noise in audio chips.

Separate pFET and nFET stacks allow different channel widths, improving compact semiconductor layout and easing fabrication.

A vertical channel with overlapping word and sensing lines increases memory density beyond planar layouts while preserving reliable cell operation.

Shield layers between data lines and TFTs cut parasitic capacitance, helping OLED sub-pixels maintain uniform luminance and image quality.

A larger transition carrier densely packs multiple LED epitaxial groups, boosting chip transfer efficiency while reducing processing steps.

Fine concavo-convex molding surfaces scatter, reflect, and absorb external light to cut glare while keeping LED package structure simple.

A trap-rich layer in an SOI semiconductor structure captures carriers at the silicon-dielectric interface to reduce parasitic conduction and signal loss.

A stepped gate electrode lets light reach the channel to clear electron traps, reducing TFT variation across large display substrates.

A sawtooth dummy pattern in the non-display area redirects solution aggregation away from edge pixels to prevent dewetting defects.

A piezoelectric adhesion structure with a position-limiting cavity enables accurate, high-volume transfer of micron-scale micro LED grains.

Switchable diffusers and shielding elements steer or diffuse light to limit off-axis viewing and reduce driver distraction in thin light emitters.

Patterned high- and low-index regions with blue colorant redirect light, suppress pixel color mixing, and reduce external reflectance.

Dummy NEPI and PEPI regions mitigate loading effects to improve across-chip and critical dimension uniformity in semiconductor fabrication.

Stacked inorganic layers with sealed openings block moisture from oxide TFTs while preserving planarization and display reliability.

Adjusting active-layer indium content and thickness shifts blue emission to 464-468 nm, reducing surface damage while sustaining luminance.

An insulating pattern between the memory layer and source structure helps dense gate stack memory maintain electrical characteristics and production yield.

Inducing particles grow conductive polysilicon channels in via holes, improving LTPS backplane TFT connections without laser annealing.

Selective interconnect removal and via layout improve display light extraction while balancing border-region stress to prevent mura defects.

Same-side anode and cathode formation simplifies micro-LED array processing, improving pixel yield, luminosity, and polarized light control.

Segmented current blocking with conductive pillars and metal-filled trenches evens LED current flow and reduces thermal stress for better yield.

Overlapping isolated charge holding sections separate signal and parasitic-light charges, reducing oblique light effects without lowering resolution.

A reflective metal-clad DTI structure isolates adjacent pixels, cutting optical cross-talk while improving quantum efficiency and image integrity.

Supplementary patterns fill gap regions between functional patterns to improve planarization flatness and luminance uniformity in display substrates.

Different optical plate regions create multiple focus planes, keeping 2D and triangulation-based 3D imaging sharp across varying depths.

By placing electrode pads over the pixel region and aligning support-substrate through-holes, this case shrinks CMOS image sensor chips.

Selective solder resist coverage narrows the PCB input region in chip-on-film packages while preserving manufacturing precision and signal transfer.

A dual-photodiode UV sensor uses a tuned silicon nitride layer to subtract dark current while preserving weak UVC sensitivity.

By placing transistors farther from the cut edge than connection electrodes, this layout reduces laser-cut damage and improves narrow-bezel panel yield.

Keeping two gate insulators within 500 Å enables simultaneous ion implantation in oxide TFT layers, improving resistance control and channel length.

Hydrophilic and hydrophobic surface patterning self-aligns microlenses on micro-LED emitters to improve front-view light output and cut power use.

An inner and outer DTI layout with a DCC region shortens photodiode overflow paths, cutting light loss and improving charge sensing accuracy.

An integrated RF enclosure shields noise and captures device emissions to identify counterfeit electronics without destructive inspection.

Precisely spaced light-emitting holes constrain LED emission positions after reflow, improving photosensitive array resolution and accuracy.

A sacrificial protective layer between microLED regions limits debris during laser transfer, improving placement accuracy and module yield.

Wet-etched pyramidal features improve image sensor light absorption while reducing plasma damage, dark current, and photo response non-uniformity.

A nucleation-inhibiting coating lowers conductive film sticking in selected areas, enabling precise mask-free patterning without debris.

A single reflective cup combines RGB emitters with a phosphor-coated blue LED to raise CRI, simplify packaging, and improve heat dissipation.

A shifted terminal and wiring layout enables uniaxial resistance welding in dual magnetic sensors, reducing interference and assembly complexity.

Separating the shared light-emitting layer from conductive layer edges prevents surface recombination and improves micro-LED emission efficiency.

A parallel micro LED chip with shared electrodes adds built-in backup emission to cut screen defects and avoid extra transfer time.

Using doped zones and conductive lines over trench isolation, this ESD diode cuts die area and RON without extra exclusion zones.

Varying main and subsidiary electrode widths controls how many light-emitting elements connect in each sub-pixel, reducing luminance differences.

A low-resistance bridge part is stacked over the spacer to cut touch electrode resistance without blocking the light emitting area.

Atom-irradiated bonding joins a reinforcement ring to the wafer edge, preventing warping and cracking during high-temperature SiC processing.

Tapered micro LED geometry, low-index regions, and a lens surface redirect and condense emitted light to cut internal loss and improve extraction.

An uneven semiconductor surface and tuned refractive index stack reduce interface reflection and multiple reflections in micro LED emission.

Stacking two oxide semiconductor transistors with polycrystalline channels simplifies fabrication while improving mobility, reliability, and integration.

Layer thickness tuning controls reflected-light interference for stacked blue, green, and red emitters, boosting full-color LED efficiency.

A floating conductive region and lightly doped anode reduce X-ray total dose effects, limiting interface states and dark current.

A stepped bezel wiring layout is masked with intermediate and lattice layers to suppress visible light reflection and improve fold durability.

An insulating pattern and bottom insulating portion guide gate contact alignment in 3D memory stacks, improving connection stability and cell density.

A dummy layer, SAM, and thermal drive-in tune the bottom gate dielectric in stacked transistors without disturbing the top gate dielectric.

A graded aluminum-containing n-type III-nitride layer cuts interface reflection and improves micro LED light extraction.

A resin mask is laser-opened and reflowed before plasma singulation to suppress wiring separation and smooth element chip side surfaces.

Photochemically stable pigments and scattering particles in pcLED side reflectors reduce pixel cross-talk, light leakage, and color shift.

Parallel capacitive elements and a higher-capacitance reference diode cut ESD-induced harmonics and disturbances in adjacent circuits.

Recessed dielectric sidewalls create a 3D capacitor in each pixel, raising capacitance density as focal plane array pixels shrink.

SOI pixel isolation and enlarged photodiode area reduce optical crosstalk and parasitic capacitance, improving conversion gain and image sensing.

Alternating positioning protrusions and conductive bumps align micro LEDs during transfer, reducing misbonding, short circuits, and open circuits.

A shielding member covers touch-sensor openings to block gas and moisture, preventing polarizer peeling and color fading.

A via-linked connecting line moves the driving circuit behind a transparent substrate, reducing panel clearance and preserving light output in spliced displays.

Adjacent subpixels share a floating diffusion region so autofocus stays accurate across high- and low-resolution modes in changing light.

UV-absorbing and IR-absorbing cover glass removes angle-sensitive reflections that cause color fringes, blooming, and chromatic aberrations.

Holes and integrated outcoupling surfaces redirect LED light in a flexible multilayer structure to limit bleed and improve illumination uniformity.

Replacing the low-resistivity SOI base with a bonded high-resistance substrate cuts RF signal loss and improves linearity without added polysilicon cost.

Separating LED chips from sensing electrodes in a layered touchpad structure preserves capacitive touch accuracy while enabling localized lighting.

A patterned micro-LED surface with controlled peak-valley height cuts laser lift-off energy, widens the process window, and preserves light extraction.

Balanced gate contact and isolation-region layout reduces local layout effects and stabilizes threshold voltage in HPC CMOS transistors.

A thin transparent protection layer replaces glued glass covers to cut light loss, improve adhesion, and block dust in photosensitive chip packaging.

Keeping photoresist on the active layer during through-hole etching cuts oxidation and damage, preserving TFT electrical performance.

Partial bonding-pad overlap increases micro LED contact area for stable mounting while reducing stress, light leakage, and viewing-angle color shift.

Using annealed transparent conductive oxide on amorphous substrates, this case shows non-polar nanorod growth that boosts quantum efficiency.

An inorganic dielectric layer between color filters and microlenses blocks moisture and thermal stress, preserving image sensor performance.

Using horizontal and vertical gate portions around the channel, this layout lowers noise and improves control without finFET-level cost.

Separating photoelectric conversion and pixel circuits across two substrates improves light shielding while preserving pixel area and dynamic range.

An integrated light conversion backlight improves color gamut without extra optical sheets, cutting display thickness and manufacturing cost.

Temperature-driven phase-changing grips enable gentle pickup, secure holding, and accurate transfer of fragile micro- and nanoscale active elements.

A vertical TFT on spacer sidewalls preserves channel length, frees pixel area for higher aperture ratio, and cuts mask count.

A multilayer nano-post lens array uses CMP and etch stop layers to separate wavelengths onto pixels and improve image sensor signal-to-noise ratio.

Splitting SPAD line arrays across multiple dice and overlapping lenses over die gaps preserves photon detection, depth sensing, and manufacturability.

A third metal pad directly contacts the SOT element to cut plug count, simplify MRAM fabrication, and protect the etched memory stack.

Segmented extension electrodes improve light extraction while protecting insulating layer openings to reduce failure risk in LED structures.

A stepped dielectric and gate-over-well-boundary layout cuts parasitic capacitance and leakage in high-voltage IC transistors.

A trapezoidal glass cover redirects sidewall reflections away from photodiodes, cutting image noise without photoabsorbent edge materials.

A reflective structure redirects incident and illumination light for lateral surface tracking at arbitrary angles without extra PCB space.

Exposed bond wire sections enlarge inter-package contact area, reduce wire sweep, and support stacked dies against bending and collapse.

Backside horizontal and vertical IC lines enable flexible pin-connector placement, reduce design rule violations, and lower IR drops.

Segmented support members and a cavity substrate reduce stress and warpage in large-area image sensors, helping preserve sensitivity.

Separated p-type and n-type regions between adjacent electrodes suppress leakage current and improve fingerprint and vein detection resolution.

Alternating overlapping subpixel electrodes raise glasses-free 3D resolution, widen viewing angles, and reduce moire and crosstalk.

A stacked black layer and reflective banks suppress ambient light reflection while directing emitted photons to improve micro LED contrast and luminance.

A dielectric-stable solvent ink helps semiconductor nanorods align by electrophoresis while limiting rapid sedimentation and improving luminance.

Vacuum injection molding forms clean substrate apertures and cured epoxy optics, improving optical package yield, adhesion, and design flexibility.

Crossed alignment electrodes use staged electric-field signals to control LED position and direction, improving display assembly precision and efficiency.

A spaced light extraction opening layout preserves OLED panel brightness at large viewing angles while reducing color shift and power loss.

A deep trench reflective isolation structure extends the light path in small pixels to boost quantum efficiency and suppress pixel crosstalk.

A patterned dopant layout in a unidirectional PIN TVS increases surge current capacity and lowers clamping voltage without simply enlarging the junction.

Interspersed dopant regions in a TVS structure raise surge current capacity while lowering clamping voltage and stabilizing low-current I-V behavior.

A resistive bottom-node leaker drains excess charge from memory cell electrodes to prevent disturb events and preserve data integrity.

A composite dielectric with corner and sidewall coverage separates top and bottom electrodes to reduce leakage current and improve semiconductor yield.

Backside interconnects formed by epitaxy, implantation, and drive-in enable full-depletion FinFETs with lower capacitance and better power efficiency.

A balanced adjacent pixel-opening ratio improves OLED ink diffusion, producing a more uniform light-emitting layer and display output.

Varying light-shielding wall heights by sub-pixel widens red emission angles and reduces large-angle color shift in micro LED panels.

A damascene cup-shaped FRAM capacitor cuts extra mask and exotic etch steps while a diffusion barrier protects ferroelectric polarization from hydrogen.

An overflow region between subpixels enables HDR imaging and autofocus in compact pixel layouts while reducing crosstalk and sensitivity differences.

Pre-encoded touch electrode cutouts carry location data, avoiding heavy coordinate computation while lowering power and cost.

Low-frame-rate monitoring cuts imaging power use, then switches to full capture when motion or a recognized image is detected.

Sequential absorber layers enable simultaneous dual-band detection on one focal plane, preserving spatial correlation without temporal interleaving.

Mixed DRAM and non-volatile memory dies in a 3D stack use NVM layers as thermal buffers to improve bandwidth, density, and power efficiency.

Non-uniform electric fields and electrostatic repulsion place micro LEDs one per groove with regular spacing, improving yield and alignment precision.

Resistive coupling between segmented trench electrodes and the anode pad limits parasitic charging to reduce forward recovery voltage.

Controlled 3D-printed frame roughness scatters reflected light inside a solid-state imaging package to reduce flare, ghosting, and image noise.

A capped solder junction overcomes oxide films between micro LED and TFT pads, enabling reliable metallic bonding with less heat-affected change.

Porous semiconductor isolation with cavity-grown single-crystal layers cuts FET off-capacitance while preserving epitaxial doped regions.

Planar metasurface arrays on sensor pixels improve fingerprint imaging, filtering, and liveness detection while shrinking optical stack height.

Adjacent pixel sets use different pupil correction amounts to keep phase-difference autofocus accurate across lens changes and zoom.