Chip-on-Film Wiring Layout for Narrower PCB Input Regions
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Solution Overview
Problem
Current chip-on-film packages face challenges in reducing the width of the input region connected to a printed circuit board, which limits their miniaturization and integration capabilities.
Innovation Solution
The design incorporates a film substrate with specific wiring patterns and solder resist layers, including exposed upper surfaces of certain wiring patterns, to reduce the width of the input region and enhance manufacturing precision, allowing for finer chip-on-film packages with improved signal transfer characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the input region width is reduced to enable miniaturization, then the size and weight of the chip-on-film package are reduced, but the manufacturing precision and signal transfer characteristics become more difficult to maintain
Solution Approach 1:
The input region is divided into multiple segments with different solder resist layer configurations. First upper wiring patterns are covered by upper solder resist layer, while second upper wiring patterns are exposed. This segmentation allows different portions of the same region to serve different functions, enabling reduced overall width while maintaining manufacturing precision through differentiated treatment of sub-regions.
Solution Approach 2:
Different areas of the input region are given different properties through selective solder resist layer application. The first upper wiring patterns have protective solder resist coverage for manufacturing stability, while the second upper wiring patterns are exposed for precise positioning and signal transfer. This local differentiation resolves the contradiction by allowing width reduction in exposed areas while maintaining precision through protected areas.
2Productivity
If the input region width is reduced to enable higher density integration, then the quantity of components per unit area increases, but the reliability of signal transfer may deteriorate
Solution Approach 1:
The wiring patterns are segmented into first and second types with different solder resist treatments. First upper wiring patterns (covered) provide stable signal paths for power and ground, while second upper wiring patterns (exposed) provide precise signal transfer paths. This segmentation enables higher integration density while maintaining reliability through functional differentiation.
Solution Approach 2:
The upper solder resist layer acts as an intermediary that selectively protects certain wiring patterns while leaving others exposed. This intermediary structure enables the coexistence of densely packed wiring patterns with reliable signal transfer, as the exposed second upper wiring patterns can be precisely controlled during manufacturing while the covered first upper wiring patterns provide stable reference paths.
Data Source
AI summary
A chip of film package comprises a film substrate having a chip mounting region, an inner lead bonding region arranged within the chip mounting region, and an outer lead bonding region spaced apart from the inner lead bonding region in a first direction, and providing upper and lower surfaces opposite to each other, a first upper wiring pattern arranged on the upper surface of the film substrate and extending in the first direction from the inner lead bonding region to the outer lead bonding region, a second upper wiring pattern spaced apart from the first upper wiring pattern in the first direction, an upper solder resist layer covering an upper surface of the first upper wiring pattern; and a lower solder resist layer covering an upper surface of the lower wiring pattern.