Stacked Memory Die Parallel Access for Bandwidth Aggregation
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Solution Overview
Problem
The use of through-die vias in stacked semiconductor memory die presents challenges such as increased die size due to area consumption, necessitating efficient schemes for coupling stacked memory die.
Innovation Solution
The implementation of a packaged semiconductor memory device with stacked memory die, where respective banks of the first and second memory cores perform memory access operations in parallel, and the first data interface provides aggregated data from these parallel operations, reducing the need for extensive through-die via usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through-die vias are used to couple stacked memory die, then memory capacity is increased, but die area is consumed and die size increases
Solution Approach 1:
The patent transitions from planar memory expansion to vertical stacking by coupling memory die through the third dimension (depth). Multiple memory die are stacked vertically and coupled using through-die vias, allowing memory capacity to increase without proportionally increasing die area. This dimensional change enables higher memory density by utilizing vertical space rather than only horizontal expansion.
2Quantity of substance
If through-die vias are used to couple stacked memory die, then memory capacity is increased, but die size increases
Solution Approach 1:
The invention employs vertical stacking architecture where memory die are arranged in multiple layers along the vertical axis. Through-die vias provide inter-layer coupling, enabling memory capacity expansion in the vertical dimension while keeping individual die lateral dimensions (length and width) relatively compact. This approach increases overall package height rather than die footprint.
3Productivity
If parallel memory access operations are performed on stacked die, then memory bandwidth is increased, but data aggregation complexity increases
Solution Approach 1:
The patent merges data output from multiple memory die by performing parallel read operations on corresponding banks across stacked die. Data from each die is combined through data aggregation logic that interleaves or consolidates the parallel data streams, effectively multiplying memory bandwidth. The merging process integrates outputs from multiple sources into a unified high-speed data output.
Solution Approach 2:
The system dynamically manages parallel access operations across stacked memory die by coordinating read/write commands to different banks. The data aggregation mechanism adaptively combines data streams from multiple die based on access patterns, enabling flexible bandwidth optimization. This dynamic coordination allows the system to maximize throughput by utilizing all available memory resources simultaneously.
Data Source
AI summary
A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.