Vertical Memory Device Bit-Line Load Equalization
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Solution Overview
Problem
Existing vertical memory devices face challenges in equalizing bit-line loads due to varying characteristics of memory cells based on distance from isolation regions, leading to decreased operating speed and performance.
Innovation Solution
The design includes a cell array with regularly arranged vertical channels and bit-lines, where bit-line contacts connect each bit-line to at least two vertical channels of different types, ensuring equalized loads by classifying channels based on distance from sub isolation regions and using bit-line contacts to balance coupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If vertical channels are regularly arranged in cell regions, then manufacturing precision is improved, but bit-line load equality deteriorates due to varying distances from isolation regions
Solution Approach 1:
The patent applies local quality by classifying vertical channels into different types based on their distance from sub isolation regions. Channels at different positions (e.g., closer to or farther from isolation regions) are assigned different characteristics, and bit-line contacts are configured to connect to specific channel types to balance the overall load. This allows each local region to have optimized properties while maintaining regular manufacturing patterns.
Solution Approach 2:
The patent changes the parameter of channel selection by connecting bit-line contacts to vertical channels of different types rather than uniform channels. By varying which channel types are connected to which bit-lines, the electrical load parameters are adjusted to achieve equality across all bit-lines, resolving the contradiction between regular arrangement and load balance.
2Reliability
If bit-line contacts connect to vertical channels of different types, then bit-line load equality is improved, but device complexity increases
Solution Approach 1:
The patent segments the vertical channels into distinct types based on their position relative to sub isolation regions. This segmentation allows for systematic classification and connection strategies, where bit-line contacts are assigned to specific channel types in a structured manner. The segmentation makes the complexity manageable by creating clear categories rather than requiring individual customization for each channel.
Solution Approach 2:
The patent applies universality by creating a standardized classification system for vertical channels that can be applied across the entire device. The same types and connection patterns are repeated throughout the array, allowing the complex classification scheme to be implemented through reusable templates rather than unique configurations for each region.
Data Source
AI summary
A vertical memory device and a method of manufacturing the same, the device including a cell array including cell regions spaced apart from each other in a second direction, each cell region including a regularly arranged plurality of vertical channels; bit-lines extending in the second direction, the bit-lines being spaced apart from each other in a first direction crossing the second direction; and bit-line contacts respectively electrically connecting the vertical channels and the bit-lines, wherein each cell region includes a sub isolation region configured to electrically isolate the cell region in the second direction, the sub isolation region extending in the first direction, the vertical channels are classified into a plurality of types according to a distance from the sub isolation region in the second direction in each cell region, and the bit-line contacts are configured to electrically connect each bit-line to at least two vertical channels having different types.