Array Substrate Through-Hole Patterning Without Active Layer Oxidation
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Solution Overview
Problem
The additional patterning process of the gate insulation layer in active display panels leads to surface oxidation and damage of the active layer, affecting the electrical performance of Thin Film Transistors (TFTs) and degrading the display performance of array substrates.
Innovation Solution
A method for manufacturing array substrates where the first photoresist layer is reserved on the active layer during the formation of the through hole in the gate insulation layer, allowing both photoresist layers to be stripped together, thereby protecting the active layer from prolonged exposure and reducing the number of photoresist removal processes, which minimizes oxidation and damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate insulation layer is patterned separately after the active layer is formed, then the gate insulation layer can be precisely defined, but the active layer surface is exposed multiple times causing oxidation and damage
Solution Approach 1:
The patent merges the gate insulation layer patterning process with the active layer patterning process by forming both layers simultaneously using a common photoresist layer. This eliminates the need for separate patterning steps, reducing the number of times the active layer surface is exposed and stripped, thereby minimizing oxidation and damage while maintaining precise definition of both layers.
2Manufacturing precision
If the photoresist layer is stripped multiple times for different patterning steps, then each layer can be precisely defined, but the manufacturing process becomes longer and more complex
Solution Approach 1:
The patent combines multiple patterning operations into a single photoresist layer that simultaneously defines both the active layer and gate insulation layer boundaries. This allows both layers to be patterned in one exposure and development cycle, with a single strip step, thereby maintaining high definition precision while significantly reducing process time and complexity.
3Ease of manufacture
If the active layer is exposed to air and photoresist removal processes multiple times, then subsequent layers can be formed, but the electrical performance of TFTs deteriorates
Solution Approach 1:
The patent forms a protective photoresist layer on the active layer before subsequent processing steps. This preliminary protective action prevents the active layer surface from being exposed to air and harsh chemicals during gate insulation layer formation, thereby preserving the electrical performance of TFTs while still enabling multi-layer formation. The photoresist acts as a protective barrier throughout the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents excessive oxidation and damage to the active layer, maintains better electrical performance of TFTs, accelerates the manufacturing process without increasing complexity, and allows for more compact array substrate designs by reducing exposure to air and photoresist removal processes.
Implementation Method 1
A first photoresist layer to-be-processed is formed on the active layer to-be-processed, and the first photoresist layer to-be-processed is exposed and developed to form a first photoresist layer
Implementation Method 2
The gate insulation layer is etched to define a through hole, where the through hole faces the signal trace
Data Source
AI summary
An array substrate, a method for manufacturing the array substrate, and a display panel are provided in the disclosure. The method for manufacturing the array substrate includes the following. A gate and a signal trace spaced apart from the gate are formed on a substrate. A gate insulation layer is formed on the substrate. An active layer to-be-processed is formed on the gate insulation layer. A first photoresist layer is formed on the active layer to-be-processed. The active layer to-be-processed is etched to form an active layer, where the first photoresist layer is on a side surface of the active layer away from the gate insulation layer. A second photoresist layer is formed on the gate insulation layer. The gate insulation layer is etched to define a through hole, where the through hole faces the signal trace.