Stacked Gate Patterning With SAM for Bottom-Only Vt Tuning
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Solution Overview
Problem
Providing multi-gate devices with multiple threshold voltages is challenging due to their small size, which limits the room for tuning threshold voltages using different work function metals, especially in stacked transistor structures like CFETs, where existing dipole engineering techniques are not entirely satisfactory.
Innovation Solution
The implementation of dipole engineering techniques using a dummy layer, self-assembled monolayer (SAM), and hard mask layer to introduce dipole dopants into the bottom gate dielectric of a bottom transistor without affecting the top gate dielectric, allowing for multi-threshold voltage tuning in stacked multi-gate devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different work function metals are used to tune threshold voltages, then multi-threshold voltage tuning is achieved, but device complexity and manufacturing difficulty increase due to the need for multiple metal layers and patterning steps
Solution Approach 1:
The patent changes the physical-chemical parameters of a single metal layer by introducing dipole moments through controlled oxidation and self-assembled monolayer formation. This allows threshold voltage tuning without adding structural complexity, as the same metal layer can be adjusted to provide different work functions for n-type and p-type transistors based on its exposure to oxidizing environments
Solution Approach 2:
A single metal layer serves multiple functions: it acts as the gate electrode for both n-type and p-type transistors and simultaneously provides different work functions for each transistor type through differential dipole engineering. This eliminates the need for separate metal layers for different transistor types, reducing overall device complexity
2Adaptability or versatility
If dipole engineering is applied to stacked transistor structures, then multi-threshold voltage tuning is enabled, but the top gate dielectric may be damaged or compromised during the process
Solution Approach 1:
The patent applies preliminary protective actions by forming a thin protective oxide layer on the metal surface before dipole layer deposition, and by carefully controlling the oxidation conditions to prevent excessive growth that could damage the underlying gate dielectric. This preliminary protection ensures the gate dielectric remains intact throughout the dipole engineering process
Solution Approach 2:
The dipole engineering is applied locally and selectively to specific metal regions corresponding to different transistor types. By controlling the spatial distribution and thickness of dipole layers only where needed, the process avoids unnecessary exposure and potential damage to gate dielectric regions that do not require threshold voltage adjustment
3Productivity
If the geometry size is reduced to increase device density, then production efficiency improves and costs decrease, but the room for tuning threshold voltages using different work function metals is limited
Solution Approach 1:
Instead of relying on geometric scaling to provide tuning range, the patent changes the electrical parameters of the gate metal by controlling dipole moment formation. This allows threshold voltage tuning capability to be maintained or even enhanced despite reduced device dimensions, as the tuning is achieved through chemical/physical modification rather than geometric variation
Solution Approach 2:
The patent transitions from spatial/geometric tuning (which is limited at small scales) to electrical/chemical tuning through dipole moments. By adding this new dimension of control through surface chemistry and dipole layer thickness, threshold voltage tuning capability is preserved in nano-sized transistors where traditional geometric approaches fail
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables flexible multi-threshold voltage tuning for stacked transistors, eliminating the need for different work function metals and preserving the integrity of the top gate dielectric, making it suitable for nano-sized transistors like FinFETs and GAA transistors.
Implementation Method 1
forming a self-assembled monolayer (SAM) on the top surface of the dummy layer
Implementation Method 2
performing a thermal drive-in process to drive a dipole dopant species from the dipole layer into the gate dielectric layer around the bottom channel member
Data Source
AI summary
Methods of forming gate structures for stacked multi-gate devices are provided. A method according to the present disclosure includes forming a gate dielectric layer to wrap around a bottom channel member and a top channel member, depositing a dipole layer over the gate dielectric layer, forming a dummy layer such that the top channel member is disposed above the top surface of the dummy layer, removing the dipole layer around the top channel member, forming a self-assembled monolayer (SAM) on the top surface of the dummy layer, depositing a hard mask layer to wrap over the top channel member, removing the SAM and the dummy layer, performing a thermal drive-in process to drive a dipole dopant species from the dipole layer into the gate dielectric layer around the bottom channel member, removing the hard mask layer, and removing the dipole layer.