3D Memory Device Multivalued Operation via Stacked Resistance Layers
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Solution Overview
Problem
Current three-dimensional memory devices with resistance change memory cells face challenges in achieving high memory density due to limitations in multivalued operation of memory cells, which restricts the ability to store data efficiently.
Innovation Solution
The memory device incorporates a resistance change film between a word line and a bit line, utilizing a nonlinear resistance layer and a resistance change layer in series to create multiple resistance states, allowing for multivalued operation by controlling the compliance current and write voltage, thereby enabling the storage of multiple resistance states in each memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If resistance change memory cells are integrated in three dimensions with a resistance change film between word line and bit line, then memory device structure is achieved, but multivalued operation capability is limited
Solution Approach 1:
The resistance change film is segmented into multiple resistance change layers (first resistance change layer, second resistance change layer, third resistance change layer) stacked in the vertical direction. Each layer can be independently controlled to achieve different resistance states, enabling multivalued operation while maintaining three-dimensional integration.
Solution Approach 2:
The patent transitions from a two-dimensional resistance change film to a three-dimensional stacked structure of multiple resistance change layers. This dimensional change allows independent control of each layer through selective voltage application, enabling multivalued operation capability that was not achievable with a single-layer film.
2Quantity of substance
If multiple resistance states are stored in each memory cell to increase memory density, then memory density is enhanced, but local bit line pitch must be increased
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple resistance change layers, allowing multiple resistance states to be stored within the same horizontal footprint. This enables increased memory density without requiring larger local bit line pitch, as the additional storage capacity is achieved through vertical stacking rather than horizontal expansion.
Solution Approach 2:
Multiple resistance change layers are nested vertically within the same memory cell structure, with each layer contributing to the overall resistance state. This nested configuration allows multiple data states to be stored in a compact vertical arrangement, increasing memory density without expanding the horizontal cell dimensions or bit line pitch.
3Adaptability or versatility
If compliance current and write voltage are controlled to create multiple resistance states, then multivalued operation is enabled, but device complexity increases
Solution Approach 1:
The patent implements dynamic control of compliance current and write voltage to selectively set different resistance states in each resistance change layer. By dynamically adjusting these parameters during write operations, the system can program multiple resistance states without requiring additional physical control lines or complex switching mechanisms, thus enabling multivalued operation with manageable complexity.
Solution Approach 2:
The patent utilizes parameter changes in compliance current and write voltage to control the resistance states of multiple layers. By varying these electrical parameters during write operations, the system can program different resistance levels in each layer, enabling multivalued operation through parameter modulation rather than through complex structural modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the storage of multivalued data, enhancing memory density without increasing the pitch of local bit lines, thus enabling miniaturization and efficient data storage.
Implementation Method 1
a first resistance change film, a second resistance change film... The first resistance change film is connected between a side surface of the second interconnect and the third interconnect. The second resistance change film is connected between a second end of the second interconnect and the fourth interconnect.
Data Source
AI summary
A memory device includes a first interconnect extending in a first direction, a second interconnect extending in a second direction crossing the first direction, a third interconnect extending in a third direction crossing a plane including the first direction and the second direction, a fourth interconnect extending in the third direction, a semiconductor member, a first resistance change film, and a second resistance change film. The semiconductor member is connected between a first end of the second interconnect and the first interconnect. The first resistance change film is connected between a side surface of the second interconnect and the third interconnect. The second resistance change film is connected between a second end of the second interconnect and the fourth interconnect.