Fin Transistor Channel Width Enhancement via 3D Inverted T-Shape
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Solution Overview
Problem
Current semiconductor devices require increased current density as integration increases, but fin transistors face limitations in achieving higher current per chip surface area due to channel width constraints.
Innovation Solution
The method involves forming fins on a semiconductor substrate with an inverted T-shaped configuration, where a gate electrode straddles the fin, and a conductive layer with a silicide layer is used to enhance current flow by increasing the channel width and reducing on-resistance, while maintaining a compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If fin transistor channel width is increased to increase current, then current per chip surface area increases, but channel width to chip surface area proportion becomes constrained
Solution Approach 1:
The patent transitions from planar 2D channel configuration to 3D vertical fin structure, enabling current flow through multiple dimensions. The fin extends vertically from the substrate surface, creating a three-dimensional current path that increases effective channel width without proportionally increasing chip surface area occupation.
Solution Approach 2:
The gate electrode wraps around the fin structure in a nested configuration, with the gate straddling the fin on both sides. This nested arrangement maximizes the gate-controlled channel width within a compact footprint, effectively increasing current capacity without linearly increasing surface area.
2Productivity
If fin transistor density is increased for high integration, then integration increases, but current per chip surface area becomes insufficient
Solution Approach 1:
The patent applies different materials and structures to different regions of the fin transistor. The source and drain regions are doped with different impurity concentrations, the gate electrode uses specific materials with optimized thickness, and sidewall insulating films are selectively positioned. This local differentiation optimizes current characteristics while maintaining high integration density.
Solution Approach 2:
The fin transistor employs composite material structures including silicon substrate with doped regions, silicon oxide insulating films, metal gate electrodes, and sidewall insulating materials. These composite materials provide optimized electrical characteristics for high current density while maintaining compact dimensions for high integration.
Data Source
AI summary
According to one embodiment, a method for manufacturing a semiconductor device includes forming a fin in an upper surface of a semiconductor substrate to extend in a first direction, forming a mask film, making a plurality of first trenches in the mask film to extend in a second direction to reach the fin, filling sidewall members into the first trenches, making a second trench by removing the mask film from a portion of a space between the sidewall members, forming a gate insulating film and a gate electrode on a surface of a first portion of the fin disposed inside the second trench, making a third trench by removing the mask film from the remaining space between the sidewall members, and causing a second portion of the fin disposed inside the third trench to become a conductor.