Patterned PIN TVS Structure for Higher Surge Current Density
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Solution Overview
Problem
Existing transient voltage suppressor (TVS) devices have limited surge current performance due to fixed PN junction size and series resistance, which restricts their high current density capabilities in protecting sensitive circuit nodes against overvoltage faults.
Innovation Solution
The TVS device incorporates a substrate with a PIN junction formed by a first and second dopant layer of opposing polarities, along with a patterned layer of the same polarity as the substrate, interspersed with a second dopant layer, creating a complex structure that enhances current rating and reduces clamping voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional PN junction structure is used with fixed doping layers, then the device structure is simple and manufacturing is easier, but the surge current performance is limited and current density capability is restricted
Solution Approach 1:
The second dopant layer is segmented into a patterned layer with isolated islands surrounded by the second layer, creating multiple discrete regions instead of a continuous structure. This segmentation increases the effective PN junction perimeter and improves surge current performance by providing multiple current paths while maintaining manageable device complexity through regular patterning
Solution Approach 2:
The patterned layer creates local variations in doping concentration and junction properties at specific regions (isolated islands) while maintaining uniformity in other areas. This local quality enhancement allows optimized current distribution and surge performance without requiring complete restructuring of the entire device
2Reliability
If the PN junction size is increased to improve current density performance, then the surge current capacity increases, but the series resistance and contact resistance also increase
Solution Approach 1:
The patterned layer introduces a spatial dimensionality change by creating isolated islands distributed across the second main surface, effectively increasing the junction perimeter area without proportionally increasing the junction area. This dimensional approach allows improved current density performance while managing series resistance through optimized current distribution paths
3Reliability
If a complex patterned layer structure is implemented to enhance surge current capacity, then the high current density performance improves, but the manufacturing process becomes more difficult
Solution Approach 1:
The patterned layer is formed by selectively doping the second main surface with controlled dopant concentration and distribution patterns. By adjusting doping parameters (concentration, depth, pattern geometry) rather than fundamentally changing the manufacturing process, surge current capacity is enhanced while keeping the doping process within standard semiconductor fabrication capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the surge current capacity and maintains stable current-voltage waveforms at low current levels, improving high current density performance compared to traditional TVS devices.
Implementation Method 1
a first dopant layer, disposed on a first main surface of the substrate, and comprising a polarity of a second type, wherein the first dopant layer forms a PIN junction with the substrate
Data Source
Figure 1~2
Figure 3A~3C
Figure 4
AI summary
A TVS device may include a substrate, comprising a polarity of a first type, a first dopant layer, disposed on a first main surface of the substrate, and comprising a polarity of a second type, wherein the first dopant layer forms a PIN junction with the substrate. The TVS device may further include a second dopant layer, disposed on a second main surface of the substrate, opposite the first main surface, the second layer comprising the polarity of the first type, and a patterned layer, disposed on the second main surface of the substrate, the patterned layer comprising the polarity of the second type, wherein the patterned layer is interspersed with the second layer.