3D Security Processor Integrating Storage and Processing
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Solution Overview
Problem
Conventional network-security systems face performance issues due to limited cores and the 'memory wall' in von Neumann architecture, which hinder efficient pattern processing for large rule and malware databases, leading to poor performance in rule enforcement and anti-malware operations.
Innovation Solution
A three-dimensional (3-D) security processor with integrated storage-processing units (SPUs) that permanently store rule/virus patterns in a 3D-M array stacked above the pattern-processing circuit, avoiding the memory wall and enabling significant performance improvements through increased storage capacity and processing power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional von Neumann architecture is used with separated processor and storage, then device complexity is reduced and ease of manufacture is improved, but processing speed deteriorates due to memory wall latency
Solution Approach 1:
The patent merges storage and processing functions into a single integrated circuit device. The storage circuit and processing circuit are fabricated together on the same semiconductor substrate, eliminating the memory wall between separate processor and storage components. This integration allows pattern data to be directly accessed and processed without external memory access delays, thereby improving pattern processing speed while accepting increased device complexity.
Solution Approach 2:
The patent transitions from a two-dimensional von Neumann architecture (separated processor and storage) to a three-dimensional integrated circuit architecture where storage and processing are vertically stacked or closely integrated on the same substrate. This dimensional change enables simultaneous access to pattern data and processing resources, dramatically reducing latency and improving processing speed at the cost of increased fabrication complexity.
2Productivity
If large rule/virus databases are stored in external memory, then storage capacity is sufficient, but processing efficiency deteriorates due to frequent memory access delays
Solution Approach 1:
The patent combines the rule/virus database storage circuit with the pattern processing circuit into a single integrated device. This merger eliminates the need for frequent external memory accesses during rule enforcement operations, as all pattern matching can be performed using data stored in the integrated storage circuit, thereby reducing memory access delays and improving overall productivity.
Solution Approach 2:
The patent pre-loads rule and virus pattern data into the integrated storage circuit before processing operations begin. This preliminary action ensures that all necessary pattern data is immediately available in the integrated storage-processing unit, eliminating the need for real-time external memory access during pattern matching operations and thus reducing processing delays.
3Productivity
If more cores are added to increase parallel processing capability, then pattern processing capacity is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges multiple processing functions into a single integrated processing circuit that can handle multiple pattern matching operations simultaneously. Rather than adding separate physical cores, the integrated circuit uses shared resources and parallel data paths within the unified architecture to achieve parallel processing capacity, thereby improving productivity without proportionally increasing device complexity.
Solution Approach 2:
The patent designs the processing circuit with multi-functional capabilities that can handle various pattern matching tasks using the same hardware resources. This universal design allows a single integrated processing unit to perform multiple pattern recognition functions simultaneously, achieving parallel processing capacity without the need for multiple specialized cores, thus controlling device complexity while improving productivity.
Data Source
AI summary
The present invention discloses a processor for enhancing network security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing rule/virus patterns and a pattern-processing circuit for performing pattern processing on an incoming network packet against said rule/virus patterns. The 3D-M array is stacked above the pattern-processing circuit.