MOS Gate Oxide Protection Circuit for Low-Noise DNW Chips
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Solution Overview
Problem
During the CMOS manufacturing process, charges can be accumulated and trapped in deep N-well (DNW) devices before they are electrically connected, leading to high voltage at the gate terminal of DNW devices, which can damage the gate oxide and result in degraded noise performance and popcorn noise in audio processing circuits.
Innovation Solution
The semiconductor chip incorporates a first oxide protection circuit with a terminal coupled to the gate terminal of a MOS transistor and a second terminal receiving a clean ground voltage, and a second oxide protection circuit with a terminal coupled to the gate terminal and a second terminal receiving a clean supply voltage, both utilizing GPPMOS and GGNMOS transistors to regulate and output voltages, thereby preventing gate oxide breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep N-well devices are used to decrease noise coupling and provide isolation, then noise performance is improved, but charges accumulated in wells can cause high voltage at gate terminal which damages gate oxide
Solution Approach 1:
The patent introduces an intermediate protection circuit between the deep N-well device gate terminal and the charge accumulation source. This protection circuit acts as a mediator that prevents direct harmful interaction by providing a controlled discharge path for accumulated charges, thereby protecting the gate oxide while maintaining the noise isolation benefits of deep N-well devices
Solution Approach 2:
The patent applies preliminary protective measures by designing the deep N-well device structure and associated protection circuits before charge accumulation can cause damage. The protection mechanism is pre-configured to counteract the harmful effect of charge accumulation, ensuring that when charges build up, they are safely discharged before reaching damaging voltage levels
2Reliability
If deep N-well devices are used to provide isolation, then noise coupling is decreased, but oxide defects occur due to high voltage at gate terminal
Solution Approach 1:
The protection circuit serves as an intermediary element that decouples the isolation function from the charge accumulation problem. It allows the deep N-well structure to maintain its isolation performance while the protection circuit handles the charge management, preventing oxide quality degradation
3Reliability
If charges are accumulated in deep N-well devices during manufacturing, then device isolation is enhanced, but high voltage damages the gate oxide of DNW devices
Solution Approach 1:
The patent introduces a protection circuit as an intermediary between the isolated deep N-well devices and the charge accumulation effects. This intermediary structure allows devices to maintain isolation while providing a controlled path for charge discharge, preventing voltage spikes from damaging gate terminals
Solution Approach 2:
The protection circuit provides beforehand cushioning by preparing a safe discharge mechanism in advance. When charge accumulation occurs during manufacturing, the pre-configured protection circuit absorbs and dissipates the energy, cushioning against voltage spikes before they can damage the gate oxide
Data Source
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AI summary
A semiconductor chip includes a metal-oxide-semiconductor (MOS) transistor, a first oxide protection circuit, and a second oxide protection circuit. The first oxide protection circuit has a first terminal coupled to a gate terminal of the MOS transistor, and further has a second terminal arranged to receive a first ground voltage, wherein a noise level of the first ground voltage is lower than a noise level of a second ground voltage defined in the semiconductor chip. The second oxide protection circuit has a first terminal coupled to the gate terminal of the MOS transistor, and further has a second terminal arranged to receive a first supply voltage, wherein a noise level of the first supply voltage is lower than a noise level of a second supply voltage defined in the semiconductor chip.