Semiconductor Memory Layer Isolation for High-Density Reliability
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Solution Overview
Problem
As the integration density of semiconductor devices increases, they often suffer from deteriorated electrical characteristics and low production yield, necessitating improvements in both areas.
Innovation Solution
A semiconductor device is designed with a gate stack comprising alternately stacked conductive patterns and interlayer insulating patterns, a channel layer surrounded by the gate stack, a memory layer surrounding the channel layer, a source structure electrically connected to the channel layer, and an insulating pattern between the memory layer and the source structure, which enhances electrical and reliability characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density of semiconductor device is increased, then operating speed and power consumption are improved, but electrical characteristics deteriorate and production yield decreases
Solution Approach 1:
The semiconductor device structure is segmented into distinct functional regions including a first region with a first insulating pattern and a second region with a second insulating pattern. This segmentation allows different areas to have optimized electrical characteristics while maintaining high integration density overall.
Solution Approach 2:
Different insulating patterns are applied to different regions of the semiconductor device based on local electrical characteristic requirements. The first insulating pattern is used in regions requiring certain electrical properties, while the second insulating pattern is used in regions requiring different electrical properties, achieving local optimization of electrical characteristics.
2Productivity
If integration density of semiconductor device is increased, then operating speed and power consumption are improved, but production yield decreases
Solution Approach 1:
The manufacturing process is segmented into distinct stages where different insulating patterns are formed in different regions. This segmentation allows for standardized processing steps that can be reliably reproduced, improving production yield while achieving high integration density.
Solution Approach 2:
Insulating patterns are formed preliminarily during the manufacturing process before final device assembly. This preliminary action ensures that electrical characteristics are optimized early in the process, preventing defects and improving production yield.
3Use of energy by moving object
If operating voltage is reduced, then power consumption is decreased, but electrical characteristics may deteriorate
Solution Approach 1:
Different insulating patterns are strategically placed in different regions to optimize electrical characteristics for low-voltage operation. The first insulating pattern in the first region and the second insulating pattern in the second region work together to maintain adequate electrical characteristics even when operating voltage is reduced for lower power consumption.
Data Source
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Figure 1B
Figure 1C
AI summary
A semiconductor device may include a gate stack including conductive patterns and interlayer insulating patterns, which are alternately stacked with each other, a channel layer surrounded by the gate stack, a memory layer surrounding the channel layer, a source structure electrically connected to the channel layer, and an insulating pattern between the memory layer and the source structure. The memory layer and the source structure are spaced apart from each other, and the insulating pattern is in contact with the channel layer, the memory layer, and the source structure.