3D Vertical Memory Cell Structure for Density and Reliability
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Solution Overview
Problem
Current memory cells face challenges in achieving high integration and reliability due to limitations in miniaturization and increased integration density.
Innovation Solution
A semiconductor memory device is designed with a three-dimensional arrangement of memory cells, featuring a word line, a sensing line, a vertical semiconductor structure with a vertical channel region, and a gate dielectric film. The vertical semiconductor structure includes sequentially stacked doped films of different conductivity types, allowing for efficient vertical channel operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase integration density, then integration density improves, but reliability deteriorates
Solution Approach 1:
The patent transitions from a planar two-dimensional memory cell structure to a three-dimensional vertical structure. The word line and sensing line are arranged vertically with overlapping regions, and the vertical channel structure extends in the thickness direction of the substrate. This dimensional change allows memory cells to be stacked vertically, significantly increasing integration density while maintaining sufficient spacing and electrical characteristics for reliable operation.
Solution Approach 2:
The patent implements a nested structure where the vertical channel structure is positioned within the overlapping region of the word line and sensing line. The gate dielectric film is formed between the vertical channel structure and the word line, creating a nested arrangement where components are integrated within each other's spatial envelope. This nesting approach maximizes space utilization and increases integration density without compromising reliability.
2Quantity of substance
If memory cells are arranged in three-dimensional structure, then integration density improves, but device complexity increases
Solution Approach 1:
The patent divides the memory cell into distinct functional segments: the word line, the sensing line, the vertical channel structure, and the gate dielectric film. Each segment has a specific function and can be independently formed and controlled during manufacturing. This segmentation simplifies the design and fabrication process compared to integrated structures, reducing device complexity while achieving high integration density through vertical stacking.
Solution Approach 2:
The vertical channel structure serves multiple functions simultaneously: it acts as the channel for charge transport, provides the interface between the word line and sensing line, and enables the three-dimensional stacking arrangement. The overlapping region of the word line and sensing line serves both as a selection mechanism and as a spatial organizer for the vertical structure. This multi-functionality reduces the number of separate components needed, thereby reducing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the downscaling of memory cells, increases integration density, and provides a compact three-dimensional array structure, overcoming density limits of bit lines in two-dimensional structures while maintaining high reliability.
Implementation Method 1
a gate dielectric film between the vertical channel region and the word line
Implementation Method 2
The vertical semiconductor structure includes a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type
Data Source
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AI summary
A semiconductor memory device is provided. The semiconductor device includes: a word line extending in a lateral direction; a sensing line apart from the word line, the sensing line overlapping the word line in a vertical direction and extending in the lateral direction; a vertical semiconductor structure passing through the word line and the sensing line in the vertical direction, the vertical semiconductor structure having a vertical channel region facing the word line in the lateral direction; and a gate dielectric film between the vertical channel region and the word line. The vertical semiconductor structure includes a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type, which are sequentially provided in the vertical direction.