Oxide TFT Display Stack With Matched Gate Insulator Thickness
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Solution Overview
Problem
Existing display devices face challenges in optimizing the resistance values of oxide semiconductor layers due to differences in gate insulating layer thickness, which affects ion implantation and channel region effectiveness, making it difficult to achieve simultaneous optimization of both layers.
Innovation Solution
The implementation of a display device structure where the first and second gate insulating layers have a thickness difference of 500 Å or less, allowing for simultaneous doping of first and second oxide semiconductor layers through ion implantation, optimizing their resistance values and channel region lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single gate insulating layer is used for both oxide semiconductor layers, then the device structure is simplified, but the thickness cannot be simultaneously optimized for both layers, worsening resistance control
Solution Approach 1:
The single gate insulating layer is segmented into two distinct layers, each with independently controllable thickness. This resolves the contradiction by allowing the first gate insulating layer to be optimized for the first oxide semiconductor layer's resistance requirements while the second gate insulating layer is optimized for the second oxide semiconductor layer's requirements.
Solution Approach 2:
The thickness parameter of the gate insulating layer is changed from a single uniform value to two different values for the first and second gate insulating layers. This parameter change enables each layer to have the specific thickness needed for optimal ion implantation and resistance control in its respective oxide semiconductor layer.
2Length of moving object
If the gate insulating layer thickness is optimized for shallow ion implantation, then the channel region length is improved, but the resistance value becomes too high, worsening conductivity
Solution Approach 1:
The gate insulating layer structure is segmented into two layers with different thicknesses, allowing the first gate insulating layer to be optimized for maintaining channel region length while the second gate insulating layer is optimized for achieving appropriate resistance values through ion implantation into the second oxide semiconductor layer.
Solution Approach 2:
Different regions of the gate insulating structure have different thickness qualities: the first gate insulating layer has a thickness optimized for channel region definition, while the second gate insulating layer has a thickness optimized for resistance control through ion implantation, allowing each local region to have the quality needed for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous optimization of resistance values for both oxide semiconductor layers, improving the effective lengths of channel regions and enhancing electron mobility, which is advantageous for high-resolution display panel manufacturing and device integration.
Implementation Method 1
simultaneous doping of first and second oxide semiconductor layers through ion implantation
Data Source
AI summary
A display device includes a substrate, a first oxide semiconductor layer on the substrate, a first gate insulating layer on the substrate and covering an upper surface of the first oxide semiconductor layer, a second oxide semiconductor layer on the first gate insulating layer, and a second gate insulating layer covering an upper surface of the second oxide semiconductor layer. The first oxide semiconductor layer includes a channel region between a source region and a drain region The second oxide semiconductor layer includes a channel region between a source region and a drain region. A difference between a thickness of the first gate insulating layer and a thickness of the second gate insulating layer is 500 Å or less.