Skip-Level Via for Aligned Semiconductor Memory Integration
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Solution Overview
Problem
The integration of high-density non-volatile semiconductor memory devices, such as MRAM, PCM, and ReRAM, faces challenges during fabrication due to difficulties in controlling via etch, leading to mis-alignment and high electrical resistance between vias and interconnect lines.
Innovation Solution
A semiconductor structure employing a skip-level via with a memory element, where the upper-most metal level is fully-aligned to the memory element, allowing for reliable insertion of magnetic tunnel junction stack layers and metallization, and incorporating a series of dielectric and metal layers to form a planarized surface and via for precise electrical contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via etching is used to connect metal layers, then via formation is achieved, but mis-alignment and high electrical resistance occur between vias and interconnect lines
Solution Approach 1:
The patent applies preliminary action by forming the skip-level via structure before completing the intermediate metal layer formation. The via etch is performed through the first dielectric layer to expose the memory element top surface before the second metal layer is deposited, ensuring precise alignment is established early in the fabrication process before subsequent layers are added
Solution Approach 2:
The patent segments the via formation process into distinct stages: first forming a via through the first dielectric layer to expose the memory element, then separately forming the second metal layer to fill and planarize the via region. This segmentation allows independent optimization of alignment precision and electrical contact properties
2Productivity
If high-density memory devices are integrated, then device density is improved, but fabrication control difficulty increases
Solution Approach 1:
The patent transitions from a conventional planar via connection to a skip-level three-dimensional via structure that connects non-adjacent metal layers. This dimensional change allows high-density memory device integration while maintaining fabrication control by establishing precise vertical alignment through the memory element top surface before completing the interconnect structure
3Reliability
If skip-level via structure is used with memory element alignment, then electrical resistance is reduced, but fabrication process complexity increases
Solution Approach 1:
The skip-level via structure utilizes preliminary action by pre-forming the via etch to expose the memory element top surface before depositing the second metal layer. This preliminary via formation establishes the precise alignment path, and subsequent metal deposition and planarization steps follow systematically, making the complex process manageable through staged execution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances design flexibility and ensures reliable electrical contact with reduced electrical resistance by aligning the memory element within a skip-level via, improving the integration of high-density memory devices.
Implementation Method 1
selectively depositing a second cap layer on the planarized top surface of the second metal layer
Implementation Method 2
depositing a third metal layer on the second dielectric layer and filling the via
Data Source
AI summary
A semiconductor structure includes a memory element disposed on a first metal layer. A first cap layer is disposed on the first metal layer and sidewalls of the memory element. A first dielectric layer is disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element. A second metal layer is disposed on the first dielectric layer and sidewalls of the first cap layer. A second cap layer is disposed on a top surface of the second metal layer. A second dielectric layer is disposed on the second cap layer. A via is in the second dielectric layer and exposes a top surface of the memory element. A third metal layer is disposed on the second dielectric layer and in the via.