Stacked pFET and nFET Layout With Independent Channel Widths
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving compactness and efficient manufacturing, particularly in stacked transistor devices where the need for uniform channel layer widths can limit performance and increase complexity.
Innovation Solution
The method involves forming stacks of layers with channel layers of semiconductor material separated by sacrificial layers, allowing for the creation of compact semiconductor devices by stacking p-type and n-type FETs separately, enabling customized channel layer widths and facilitating easy manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If uniform channel layer widths are used in stacked transistor devices, then manufacturing is simplified, but device performance and space optimization are limited
Solution Approach 1:
The patent segments the stacked transistor structure into separate pFET and nFET stacks, allowing each stack to have independently optimized channel layer widths. The pFET stack uses narrower channel layers while the nFET stack uses wider channel layers, enabling performance optimization for each transistor type without requiring uniform widths across the entire device.
Solution Approach 2:
The patent applies local quality by allowing different channel layer widths in different regions of the stacked device. Specifically, the pFET stack has a first channel layer width optimized for p-type transistors, while the nFET stack has a second channel layer width optimized for n-type transistors, enabling each region to have the specific properties needed for its function.
2Area of stationary object
If pFETs and nFETs are stacked together, then area efficiency is improved, but manufacturing complexity increases due to uniform width requirements
Solution Approach 1:
The patent divides the stacked transistor device into separate pFET and nFET stacks that can be manufactured independently and then combined. This segmentation allows each stack to be optimized for its specific transistor type while maintaining the area efficiency benefits of vertical stacking.
Solution Approach 2:
The patent transitions from a planar configuration to a three-dimensional stacked architecture, allowing pFETs and nFETs to be arranged vertically rather than horizontally. This dimensional change enables area efficiency while the separate stack design manages the complexity of different channel width requirements.
3Adaptability or versatility
If separate stacks for pFETs and nFETs are used, then performance optimization is improved, but device area increases
Solution Approach 1:
The patent uses vertical stacking to combine separate pFET and nFET stacks in the third dimension, allowing performance optimization for each transistor type while minimizing the planar footprint. The stacked architecture enables independent optimization of each stack without increasing the overall device area significantly.
Solution Approach 2:
The patent implements a nested structure where pFET stacks and nFET stacks are positioned adjacent to each other in a compact arrangement, with each stack containing multiple transistor layers nested vertically. This nesting enables separate optimization while maintaining compact overall dimensions.
Data Source
Figure 1
Figure 2a~2c
Figure 3a~4a
AI summary
A method for forming a semiconductor device (1), the method comprising: forming a plurality of stacks of layers (10a, 10b) on a substrate (4), the stacks of layers being laterally spaced apart; converting each stack of layers (10a, 10b) into a stack of field-effect transistors (60a, 60b), FETs, each stack of FETs (60a, 60b), comprising a first FET (61) at the lower section (15a, 15b) of the stack of layers (10a, 10b) and a second FET (62) at the upper section (16a, 16b) of the stack of layers (10a, 10b), the first stack of layers (10a) being converted into a first stack of FETs (60a), the first (61) and second (62) FETs of the first stack of FETs being p-type FETs, the second stack of layers (10b) being converted into a second stack of FETs (60b), the first (61) and second (62) FETs of the second stack of FETs (60b) being n-type FETs.