Vertical CMOS Image Sensor Grounded Dummy Moats
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Solution Overview
Problem
The existing vertical-type CMOS image sensors face issues with incomplete grounding and gettering, particularly on the lower epitaxial layers and semiconductor substrate, leading to noise and insufficient removal of metal impurities, which degrades image quality and increases noise and leakage current.
Innovation Solution
The solution involves expanding the source and drain regions by performing a p+ type source and drain impurity ion implantation process on the silicon substrate and epitaxial layers, forming grounded dummy moats connected to external terminals to enhance grounding and gettering effects across all epitaxial layers, ensuring comprehensive metal ion removal and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a vertical-type CMOS image sensor is used to improve pixel integration density, then the degree of integration is improved, but grounding and gettering is insufficient on lower epitaxial layers and substrate, leading to increased noise and leakage current
Solution Approach 1:
The patent divides the grounding and gettering function into multiple segments by creating separate dummy moat regions at different vertical levels (first dummy moat in substrate, second dummy moat in first epitaxial layer, third dummy moat in second epitaxial layer). Each dummy moat independently provides grounding and gettering for its specific layer, ensuring comprehensive coverage throughout the vertical structure without compromising pixel integration density.
2Reliability
If dummy moat regions are added to improve grounding and gettering, then noise and leakage current are reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the dummy moat regions: they simultaneously provide grounding (electrical connection to ground potential), gettering (trapping of metal impurities), and isolation (separation of photodiodes). By combining these functions into single structural elements rather than adding separate components, the patent reduces noise and leakage current without proportionally increasing device complexity.
3Reliability
If p+ type dummy regions are added to improve gettering effect, then metal impurity removal is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent performs p+ type ion implantation into dummy moat regions during the manufacturing process to pre-load these regions with gettering atoms before metal impurities can contaminate the device. This preliminary action ensures that the dummy moats are ready to immediately trap and remove metal impurities, enhancing gettering effectiveness while integrating the process into the existing manufacturing flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively improves grounding and gettering, reducing noise and leakage current, thereby enhancing image quality and minimizing faulty pixels, such as white or dead pixels, by ensuring all epitaxial layers and the substrate are adequately grounded and cleaned of metal contaminants.
Implementation Method 1
performing a p+ type source and drain impurity ion implantation process on the silicon substrate and epitaxial layers
Implementation Method 2
enhance grounding and gettering effects across all epitaxial layers, ensuring comprehensive metal ion removal
Data Source
AI summary
Embodiments relate to a vertical-type CMOS image sensor, a method of manufacturing the same, and a method of gettering the same, in which source and drain regions are expanded to improve grounding and gettering effects. In embodiments, the vertical-type CMOS image sensor may include a silicon substrate, a first photodiode formed in a prescribed part of the silicon substrate, a first epitaxial layer formed on the silicon substrate, a second photodiode formed on the first epitaxial layer to overlap the first photodiode, a second epitaxial layer formed on the first epitaxial layer, a third photodiode formed on the second epitaxial layer to overlap the second photodiode, and first to third grounded dummy moats formed by implanting impurities into uniform parts on the silicon substrate, the first epitaxial layer, and the second epitaxial layer.