CMOS Image Sensor Pad Layout for Smaller Chip Footprint
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Solution Overview
Problem
In solid state imaging devices, the conventional method of forming electrodes on the back surface increases chip size due to the need for electrode pads outside the pixel region, making it difficult to significantly reduce the device size.
Innovation Solution
A solid state imaging device with a semiconductor substrate, a laminated wiring layer, and a support substrate where electrode pads are positioned to overlap the pixel region, and through-holes are formed in the support substrate to facilitate external electrical connections, allowing for a more compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If electrode pads are arranged outside the pixel region on the back surface, then external electrical connections can be established, but the chip size increases due to the additional area required for electrode pads
Solution Approach 1:
The patent transitions from planar arrangement of electrode pads to three-dimensional stacking by placing electrode pads on multiple layers (first wiring layer and second wiring layer) at different heights, enabling external connections without increasing chip footprint area
Solution Approach 2:
The patent embeds electrode pads within the pixel region by nesting them across multiple wiring layers, where the first electrode pads and second electrode pads are positioned at different vertical levels, effectively utilizing the vertical dimension to accommodate connection structures within the existing chip area
2Ease of manufacture
If through-holes are formed in the support substrate to connect electrode pads, then external electrical connections are enabled, but the structural integrity and stability may be compromised
Solution Approach 1:
The patent extracts the through-hole formation from the support substrate and relocates the connection structure to the wiring layers, where electrode pads are formed on the first and second wiring layers without penetrating the support substrate, thereby maintaining substrate integrity
Solution Approach 2:
The patent introduces wiring layers as intermediary structures between the electrode pads and external connections, allowing electrical connections to be established through conductive pathways in the wiring layers rather than direct through-holes in the support substrate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a further reduction in chip size without compromising pixel placement or image quality, while also stabilizing power supply and reducing power consumption.
Implementation Method 1
a support substrate that is bonded to the wiring layer and supports the semiconductor substrate
Data Source
AI summary
The present disclosure relates to a solid state imaging device capable of further decreasing a chip size, a solid state imaging device manufacturing method, and an electronic apparatus. A solid state imaging device includes: a semiconductor substrate with a pixel region on which a plurality of pixels is arranged in a planar manner; a wiring layer that is laminated on the semiconductor substrate and is provided with wiring connected to the plurality of pixels; and a support substrate that is bonded to the wiring layer. A plurality of electrode pads used to be electrically connected to an outside is arranged at positions overlapping the pixel region in the wiring layer, and through-holes are provided at positions corresponding to the plurality of electrode pads in the support substrate. The present technology can be applied to, for example, a back side irradiation type CMOS image sensor of a wafer level CSP.