Porous Semiconductor Isolation Structure for Low Off-Capacitance FETs
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Solution Overview
Problem
Conventional field-effect transistors exhibit high off-capacitance, which negatively impacts device performance in semiconductor device structures, particularly in CMOS processes used for radio-frequency integrated circuits.
Innovation Solution
A semiconductor device structure is formed using a porous semiconductor material as a substrate with a single-crystal semiconductor layer in cavities, where the porous material serves as a crystalline template for epitaxial growth of doped single-crystal layers, reducing off-capacitance by creating a shallow trench isolation region and utilizing epitaxial growth to form doped regions within these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional field-effect transistor structures are used, then device fabrication is straightforward, but off-capacitance is high which deteriorates device performance
Solution Approach 1:
The semiconductor structure is segmented into multiple layers: a porous semiconductor substrate layer and a separate single-crystal semiconductor layer formed in cavities within the porous layer. This segmentation allows the porous substrate to provide mechanical support while the single-crystal layer provides high-quality electrical characteristics, thereby reducing off-capacitance and improving device performance without complicating the overall fabrication process
Solution Approach 2:
Different regions of the semiconductor structure are assigned different material qualities: the porous semiconductor substrate provides mechanical stability and ease of fabrication, while localized single-crystal semiconductor regions embedded in cavities provide low off-capacitance. This local quality differentiation allows each region to optimize its function, reducing harmful off-capacitance effects while maintaining fabrication simplicity
2Object-generated harmful factors
If porous semiconductor material is used as substrate, then off-capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The porous semiconductor substrate is prepared in advance with a regular array of cavities formed before the single-crystal semiconductor layers are deposited. This preliminary structuring of the substrate allows subsequent epitaxial growth to proceed efficiently in pre-defined locations, reducing manufacturing complexity while maintaining the off-capacitance reduction benefits of the porous structure
Solution Approach 2:
The porous semiconductor substrate acts as an intermediary between the substrate preparation process and the final device formation. It provides a pre-fabricated template with cavities that guides the formation of single-crystal layers, simplifying the overall manufacturing process while enabling the off-capacitance reduction achieved by the porous structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces off-capacitance in field-effect transistors, enhancing performance metrics and improving the overall efficiency of semiconductor device structures.
Implementation Method 1
the porous material serves as a crystalline template for epitaxial growth of doped single-crystal layers
Data Source
AI summary
Semiconductor device structures with device isolation and methods of forming a semiconductor device structure with device isolation. The structure comprises a semiconductor substrate, a first semiconductor layer on the semiconductor substrate, a second semiconductor layer in a cavity in the first semiconductor layer, and a device structure including a doped region in the second semiconductor layer. The first semiconductor layer comprises a porous semiconductor material, and the second semiconductor layer comprises a single-crystal semiconductor material.