3D 2T-1C Memory Cell Layout for High-Density DRAM Scaling
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Solution Overview
Problem
The scalability of Dynamic Random Access Memory (DRAM) is limited by the difficulty in incorporating capacitors with sufficiently high capacitance into highly-integrated architectures, particularly in 1T-1C configurations, necessitating the development of new memory cell configurations suitable for modern memory architectures.
Innovation Solution
The implementation of 2T-1C memory cell configurations where two transistors and one capacitor are vertically stacked, allowing for increased integration by comparing electrical properties of comparative bitlines to ascertain memory states, thereby omitting the need for a reference bitline, and enabling high-density memory cell packing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 1T-1C memory cell configuration is used, then structural simplicity is achieved, but scalability and integration density are limited due to difficulty in incorporating capacitors with sufficiently high capacitance into highly-integrated architectures
Solution Approach 1:
The patent transitions from planar 1T-1C memory cell layout to a three-dimensional stacked configuration where two transistors and one capacitor are vertically arranged. This dimensional change allows the capacitor to be positioned above the transistors, enabling higher integration density while maintaining sufficient capacitance values in highly-integrated architectures.
Solution Approach 2:
The patent combines multiple functional components (two transistors and one capacitor) into a single vertically-integrated memory cell structure. By merging these components in a stacked configuration, the design achieves both the functional requirements of the memory cell and the space efficiency needed for high integration density.
2Quantity of substance
If capacitor size is increased to achieve sufficiently high capacitance, then capacitance requirement is met, but area occupied by capacitor increases reducing integration density
Solution Approach 1:
The patent moves the capacitor from a planar arrangement to a vertical stack, utilizing the third dimension (height) to accommodate the capacitor above the transistors. This allows the capacitor to achieve sufficiently high capacitance without occupying excessive lateral area, thereby maintaining high integration density.
Data Source
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AI summary
A memory cell comprising first and second transistors vertically displaced relative to one another; and a capacitor disposed to be vertically between the first and second transistors, the capacitor having a first node electrically coupled with a source/drain region of the first transistor, having a second node electrically coupled with a source/drain region of the second transistor, and having capacitor dielectric material between the first and second nodes.