SOI RF Substrate Replacement for Lower Signal Loss and Linearity
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Solution Overview
Problem
Existing semiconductor-on-insulator (SOI) substrates used for RF devices suffer from signal loss and degraded linearity due to low resistivity, which is costly to improve with additional polysilicon layers, necessitating a cost-effective solution for enhanced performance.
Innovation Solution
A method involving bonding a device wafer with an SOI substrate to a high-resistance substrate, replacing the low-resistance lower substrate with a high-resistance material, thereby reducing signal induction and improving linearity without increasing costs by thinning the device wafer and using a high-resistance substrate with resistivity higher than 100 Ω·cm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon layer is added between the lower substrate and the buried insulator layer to increase resistivity, then signal loss is reduced and signal linearity is enhanced, but manufacturing cost increases significantly
Solution Approach 1:
The patent extracts and removes the problematic lower substrate with low resistivity from the SOI structure. By thinning the device wafer from the backside, the lower substrate is completely removed, eliminating the source of signal loss and linearity degradation without requiring the addition of expensive polysilicon layers.
Solution Approach 2:
The patent changes the resistivity parameter of the substrate by replacing the low-resistivity lower substrate (8-10 Ω·cm) with a high-resistivity substrate (greater than 1000 Ω·cm). This parameter change is achieved through substrate replacement rather than material addition, thereby improving signal linearity without increasing manufacturing complexity or cost.
2Stability of the object's composition
If the lower substrate is doped with ions to reduce resistivity to 8-10 Ω·cm, then substrate consistency is improved, but signal loss increases and linearity degrades
Solution Approach 1:
The patent changes the resistivity parameter from low (8-10 Ω·cm) to high (greater than 1000 Ω·cm) by replacing the doped lower substrate with a high-resistivity substrate. This eliminates the trade-off between consistency and linearity, as the high-resistivity substrate provides both compositional stability and superior RF performance.
3Reliability
If the device wafer is thinned from the backside to remove the lower substrate, then signal loss is reduced and linearity is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent extracts the problematic lower substrate by thinning the device wafer from the backside. This removal process eliminates the source of RF signal loss and linearity degradation. The thinning process is a standard semiconductor manufacturing technique that adds minimal complexity compared to the alternative of adding polysilicon layers.
Solution Approach 2:
Instead of adding material (polysilicon layer) to improve performance from the front side, the patent works from the back side by removing material. This inverted approach of removing the lower substrate rather than adding layers simplifies the overall structure and reduces manufacturing complexity while achieving the desired RF performance improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces signal loss and enhances signal linearity in RF devices while maintaining cost-effectiveness by using a less expensive SOI substrate configuration, eliminating the need for additional polysilicon layers and minimizing cost increments.
Implementation Method 1
bonding the device wafer at a front side thereof to the carrier wafer
Implementation Method 2
removing at least the lower substrate through thinning the device wafer from a backside thereof
Implementation Method 3
bonding the device wafer at the backside thereof to the high-resistance substrate
Data Source
AI summary
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes: providing a device wafer and a carrier wafer, the device wafer including an SOI substrate comprising, stacked from the bottom upward, a lower substrate, a buried insulator layer and a semiconductor layer; bonding the device wafer at a front side thereof to the carrier wafer; removing at least the lower substrate through thinning the device wafer from a backside thereof, wherein the backside of the device wafer opposes the front side thereof; and providing a high-resistance substrate and bonding the device wafer at the backside thereof to the high-resistance substrate, the high-resistance substrate having a resistivity higher than that of the lower substrate. With the present disclosure, lower signal loss and improved signal linearity can be achieved while avoiding a significant cost increase.