Gate-Over-Well-Boundary Transistor Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
In high voltage integrated circuit (IC) structures, forming a gate structure without creating parasitic capacitance or conduction issues between adjacent conductors is challenging, particularly due to the proximity of gate contacts, which can lead to unwanted leakage and short circuits.
Innovation Solution
A transistor structure is designed with a doped well region having a first doped well abutting a second doped well at a boundary, featuring a dielectric layer with varying heights and gate structures positioned over these regions to mitigate parasitic capacitance, including a first gate structure over the boundary between the doped wells and a second gate structure over the second doped well, with an optional third gate structure laterally positioned between the first and second gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate structures are formed in high voltage IC structures, then electrical control and switching functionality are achieved, but parasitic capacitance and conduction between adjacent conductors increase, leading to leakage and short circuits
Solution Approach 1:
An intermediate dielectric layer is introduced between the gate structure and adjacent conductors to reduce parasitic capacitance and prevent unwanted conduction. This dielectric layer acts as a mediator that maintains electrical isolation while allowing the gate structure to perform its control function, thereby resolving the contradiction between achieving electrical control and minimizing parasitic effects.
Solution Approach 2:
The gate structure is extended into a third dimension by forming an extended drain region that protrudes from the substrate surface. This dimensional change allows the gate to achieve better electrical control over the drain region while maintaining increased spacing from adjacent conductors in the planar dimension, thus reducing parasitic capacitance and conduction.
2Area of stationary object
If gate structures are positioned close to other conductors to reduce device area, then device integration density increases, but unwanted parasitic capacitance and leakage between adjacent structures increase
Solution Approach 1:
The extended drain region is formed by depositing additional semiconductor material that protrudes from the substrate surface, creating a three-dimensional structure. This allows the gate to extend closer to adjacent conductors in the planar view without actually reducing the vertical spacing, thereby maintaining low parasitic capacitance while achieving high integration density.
Solution Approach 2:
The device structure is segmented into multiple regions with different heights and functions: the extended drain region protruding from the substrate, the gate structure positioned above it, and the isolation dielectric layer surrounding them. This segmentation allows each component to be optimized independently for its specific function while working together to achieve both high density and low parasitic effects.
3Speed
If extended drain regions are formed to improve transistor performance, then switching speed and breakdown voltage increase, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The extended drain region is formed during the preliminary stages of device fabrication, before the gate structure is fully assembled. By preparing the extended drain region in advance and positioning it correctly, subsequent processing steps become simpler and more straightforward, reducing overall device complexity despite the advanced functionality achieved.
Data Source
AI summary
A transistor structure is disclosed. The transistor structure includes a dielectric layer that has a thinner portion over a first doped well and a second doped well, and a thicker portion adjacent the thinner portion and over the second doped well. The thicker portion has a height greater than the thinner portion above the doped wells. The transistor includes a first gate structure on the thinner portion and a second gate structure on the thicker portion of the dielectric layer. The transistor may include a third gate structure on the thicker portion.