Split-Gate NVM Select-Gate Erase Voltage Polarity Adjustment
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Solution Overview
Problem
Split-gate non-volatile memory cells experience break-down failures during erase operations due to high electric fields between the select gate and control gate, which is challenging to mitigate without affecting the gate stack operation.
Innovation Solution
Adjusting the select-gate erase voltage to have the same polarity as the control-gate voltage during erase operations, reducing the electric field by applying a voltage that is either greater or less than the read voltage, depending on the bias type, to minimize break-down failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large positive or negative erase voltage is applied to the control gate during erase operations, then charge is effectively removed from the charge storage layer, but high electric fields are generated between the select gate and control gate causing break-down failures
Solution Approach 1:
The patent introduces an intermediary voltage adjustment mechanism where the select gate voltage is modified during erase operations. Instead of applying the full erase voltage directly to the control gate, a voltage divider or voltage adjustment circuit is used to distribute the voltage stress, with the select gate receiving an adjusted voltage that reduces the electric field between gates while still enabling effective erase through the charge storage layer.
Solution Approach 2:
The patent changes the voltage parameter of the select gate during erase operations. The select gate voltage is adjusted from its normal read level to a modified level that reduces the electric field stress between the select gate and control gate. This parameter change allows the control gate to receive the full erase voltage while the select gate experiences reduced stress, preventing break-down failures.
2Object-affected harmful factors
If the thickness of the gap dielectric layer between control gate and select gate is increased to reduce break-down failures, then electric field stress is reduced, but gate stack operation is adversely affected and additional processing steps are required
Solution Approach 1:
Instead of changing the physical dimension (thickness) of the gap dielectric layer, the patent changes the electrical parameter (voltage) applied to the select gate during erase operations. This voltage adjustment achieves the same protective effect against break-down failures without modifying the gate stack structure or requiring additional processing steps to add or modify dielectric layers.
Solution Approach 2:
The patent applies preliminary voltage adjustment to the select gate before the erase operation proceeds. By pre-adjusting the select gate voltage to an appropriate level, the system prevents break-down failures from occurring in the first place, rather than relying on structural modifications that would require additional processing steps.
3Object-affected harmful factors
If the select gate voltage is adjusted during erase operations to have the same polarity as the control gate voltage, then the electric field between gates is reduced and break-down failures are minimized, but voltage control complexity increases
Solution Approach 1:
The patent designs the voltage adjustment mechanism to serve multiple functions: it adjusts the select gate voltage during erase operations to prevent break-down failures, while also maintaining compatibility with normal read and program operations. This multi-functional approach reduces the need for separate dedicated circuits, thereby minimizing the increase in voltage control complexity.
Solution Approach 2:
The patent implements dynamic voltage adjustment where the select gate voltage is automatically modified based on the operation mode (read, program, or erase). During erase operations, the select gate voltage dynamically changes to have the same polarity as the control gate voltage, while returning to normal levels during other operations. This dynamic adaptation allows the system to handle voltage control complexity only when necessary.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces select-gate to control-gate break-down failures while maintaining efficient erase operations, even with discrete charge storage layers like silicon nanocrystals, without degrading erase speed performance.
Implementation Method 1
the control-gate voltage (VCG) is set to a positive erase voltage (VE), which is a large positive voltage used to remove charge from the discrete charge storage layer 132
Implementation Method 2
Adjusting the select-gate erase voltage to have the same polarity as the control-gate voltage during erase operations, reducing the electric field by applying a positive or negative bias
Data Source
AI summary
Methods and systems are disclosed for erasing split-gate non-volatile memory (NVM) cells using select-gate erase voltages that are adjusted to reduce select-gate to control-gate break-down failures. The adjusted select-gate erase voltages provide bias voltages on the select-gates that are configured to have the same polarity as the control-gate erase voltages applied during erase operations and that are different from select-gate read voltages applied during read operations. Certain additional embodiments use discrete charge storage layers for the split-gate NVM cells and include split-gate NVM cells having gap dielectric layer thicknesses that are dependent upon control gate dielectric layer widths.