Backside Conducting Line Layout for Flexible IC Pin Connections
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Solution Overview
Problem
The miniaturization of integrated circuits poses design and manufacturing challenges, particularly in ensuring design rule compliance and flexibility in positioning pin-connectors without generating design rule violations, which affects the layout and functionality of NOR gate circuits and other logic circuits.
Innovation Solution
The implementation of backside horizontal and vertical conducting lines with specific configurations, such as extended conducting lines and local two-dimensional conducting lines with varying widths, allows for flexible positioning of pin-connectors while maintaining design rule compliance, thereby enhancing the layout area coverage and reducing IR drops in integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional conducting line configurations are used, then manufacturing simplicity is maintained, but pin-connector positioning flexibility is limited and design rule violations occur
Solution Approach 1:
The conducting line configuration is segmented into multiple types (straight conducting lines, extended conducting lines, local two-dimensional conducting lines) that can be selectively applied to different regions of the circuit layout. This segmentation allows pin-connectors to be positioned flexibly in backside regions while maintaining design rule compliance in critical areas.
Solution Approach 2:
The patent introduces conducting lines that extend into the backside region of the substrate, utilizing the third dimension (depth/layer) to resolve the contradiction. By positioning conducting lines in both frontside and backside regions, the design achieves greater positioning flexibility without violating planar design rules.
2Area of stationary object
If pin-connectors are positioned to maximize layout area coverage, then circuit functionality is improved, but design rule violations may occur
Solution Approach 1:
The patent utilizes the backside region of the substrate to position conducting lines and pin-connectors, effectively adding a vertical dimension to the layout. This allows maximum area coverage to be achieved without violating frontside design rules, as the additional conducting lines are positioned in the backside region where different design rules apply.
3Loss of energy
If conventional conducting line configurations are used, then manufacturing simplicity is maintained, but IR drops increase
Solution Approach 1:
The conducting line network is segmented into multiple parallel paths including straight conducting lines, extended conducting lines, and local two-dimensional conducting lines. This segmentation creates multiple current pathways that reduce current density in any single line, thereby reducing IR drops while distributing the complexity across different line types.
Solution Approach 2:
The patent merges multiple conducting line configurations (straight lines, extended lines, and local two-dimensional lines) into a unified conducting line network. This combination creates redundant current paths that reduce overall resistance and minimize IR drops in the circuit.
Data Source
AI summary
An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.