Vertical Micro-LED Structure for Leakage and Charge Crowding Control

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Solution Overview

Problem

The reduction in size of optoelectronic devices, such as LEDs, leads to performance issues like higher leakage current, charge crowding, and non-radiative recombination due to defects and material limitations, which are not effectively addressed by existing technologies.

Innovation Solution

The development of a method for fabricating an array of micro optoelectronic devices with a monolithic active layer, featuring a backplane with a driving circuit, bottom and top contacts, and a common top electrode, along with the use of metal-insulator-semiconductor (MIS) structures to modulate the internal electric field and control lateral current flow, allowing for improved conductivity and reduced defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the size of optoelectronic devices is reduced to increase pixel density, then device area is improved, but device performance deteriorates due to higher leakage current, charge crowding, and non-radiative recombination

Engineering Contradiction:
Improvedevice areaVSAvoiddevice performance
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The device structure is segmented into distinct functional regions including n-type contact regions, p-type contact regions, and active regions separated by isolation structures. This segmentation allows independent optimization of each region to mitigate size-related performance issues while maintaining small overall device footprint for high pixel density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the device are assigned different material compositions and doping concentrations tailored to their specific functions. The n-type and p-type contact regions have optimized local properties to reduce leakage current, while the active region maintains high radiative efficiency. This local quality optimization ensures reliable performance even at reduced device sizes.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If device size is reduced, then pixel density is improved, but charge crowding at interfaces increases leading to performance degradation

Engineering Contradiction:
Improvepixel densityVSAvoidcharge crowding
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

Isolation structures are introduced as intermediary elements between adjacent n-type and p-type regions. These isolation structures prevent direct charge crowding at interfaces by providing electrical separation, thereby eliminating the harmful charge accumulation effect while allowing the device to maintain reduced dimensions for high pixel density.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If device size is reduced, then higher pixel density is achieved, but unwanted recombination such as Auger and nonradiative recombination increases

Engineering Contradiction:
Improvepixel densityVSAvoidnon-radiative recombination
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The doping concentrations, layer thicknesses, and material compositions are precisely adjusted as key parameters to optimize radiative recombination efficiency. By controlling these parameters, the device maintains high internal quantum efficiency even at reduced sizes, minimizing Auger and nonradiative recombination losses while achieving high pixel density.

Inventive Principle:
Principle #35Parameter changes

4Ease of manufacture

If conventional bonding methods using heat and pressure are used, then device layers can be bonded to system substrate, but device performance deteriorates due to vertical current flow disruption

Engineering Contradiction:
Improvebonding processVSAvoidcurrent flow functionality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The device structure is pre-configured with optimized contact regions and current flow paths before bonding. The n-type and p-type contact regions are positioned and dimensioned in advance to ensure that vertical current flow is maintained through the bonded interface. This preliminary structural optimization ensures that subsequent bonding processes do not disrupt the vertical current flow functionality.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the performance of micro optoelectronic devices by reducing leakage current, non-radiative recombination, and charge crowding, resulting in higher resolution, brightness, and cost-effectiveness for LED displays while maintaining device efficiency and uniformity.

Implementation Method 1

use of metal-insulator-semiconductor (MIS) structures to modulate the internal electric field and control lateral current flow

Methodology Applied
Scientific EffectElectric Field: Electric Field

Implementation Method 2

a common top electrode connected to all of the top contacts

Methodology Applied
Scientific EffectElectrical Conduction: Conduction (electrical)

Data Source

PatentUS12256583B2Vertical solid-state devices
Publication Date: 2025.03.18 VUEREAL INC
  • US12256583B2 patent drawing
  • US12256583B2 patent drawing
  • US12256583B2 patent drawing

AI summary

As the pixel density of optoelectronic devices becomes higher, and the size of the optoelectronic devices becomes smaller, the problem of isolating the individual micro devices becomes more difficult. A method of fabricating an optoelectronic device, which includes an array of micro devices, comprises: forming a device layer structure including a monolithic active layer on a substrate; forming an array of first contacts on the device layer structure defining the array of micro devices; mounting the array of first contacts to a backplane comprising a driving circuit which controls the current flowing into the array of micro devices; removing the substrate; and forming an array of second contacts corresponding to the array of first contacts with a barrier between each second contact.