SOI Image Sensor Pixel Structure for Optical Interference Isolation
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Solution Overview
Problem
Image sensors, particularly CMOS image sensors, face challenges in pixel performance due to light interference affecting photodiodes and electrical signals, leading to image deformation issues with high-speed moving objects and optical interference between adjacent photodiodes.
Innovation Solution
The use of a silicon-on-insulator (SOI) substrate in the image sensor design, which includes a silicon base, doped regions, isolation structures, a transistor, interconnect structure, passivation layer, and microlens, results in a photodiode with a large light-receiving area and reduced parasitic capacitance, enhancing pixel performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional CMOS image sensor structure is used, then the manufacturing process is simple and mass production is feasible, but the pixel performance is degraded due to optical interference between adjacent photodiodes and deformation of images of high-speed moving objects
Solution Approach 1:
The pixel layer is divided into multiple independent photodiodes with individual readout circuits, allowing each pixel to operate independently and reducing optical interference between adjacent pixels through physical separation and isolation structures
Solution Approach 2:
Isolation structures are introduced between adjacent photodiodes to block optical interference, and the silicon-on-insulator substrate provides an intermediate insulating layer that reduces parasitic capacitance and improves signal isolation
2Use of energy by moving object
If the photodiode light-receiving area is increased to improve light sensitivity, then more light can be captured, but the device area increases and integration density decreases
Solution Approach 1:
Multiple functional components (photodiode, transfer gate, reset gate, readout circuit) are merged into a highly integrated pixel structure that maximizes the light-receiving area while minimizing the total pixel area through three-dimensional stacking and layered integration
Solution Approach 2:
The pixel structure transitions from a two-dimensional planar layout to a three-dimensional stacked architecture, allowing the photodiode to occupy the maximum area for light reception while other components are arranged in vertical layers above and below
3Measurement precision
If a silicon-on-insulator substrate is used to reduce parasitic capacitance and improve pixel performance, then conversion gain increases, but the manufacturing complexity increases
Solution Approach 1:
The substrate structure is changed from conventional bulk silicon to silicon-on-insulator, fundamentally altering the electrical parameters by reducing parasitic capacitance and improving isolation, which directly enhances conversion gain and pixel performance
Solution Approach 2:
The silicon-on-insulator substrate combines silicon active layers with insulator layers (such as buried oxide), creating a composite material structure that provides both electrical isolation and mechanical support while enabling reduced parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves pixel performance by increasing the light-receiving area and potential well capacity, resulting in higher conversion gain and better image sensing capabilities while minimizing optical interference.
Implementation Method 1
When light from the outside enters the image sensor, the pixel performance of the image sensor is affected by the amount of light entering the photodiode
Data Source
AI summary
Provided are an image sensor and a manufacturing method thereof. In the image sensor, an insulating layer and a first silicon layer are sequentially on a silicon base. A first isolation structure is in the first silicon layer to define an active area (AA). A doped region is in a part of the first silicon layer in the AA and in a part of the silicon base thereunder. A second silicon layer is in a part of the first silicon layer in the AA and extends into the silicon base. An interconnection structure is on the first silicon layer and electrically connected with a transistor. A second isolation structure is in the silicon base under the first isolation structure and connected to the insulating layer. A passivation layer surrounds the silicon base and is connected to the doped region. A microlens is on the silicon base.