Non-Uniform Pitch Routing Tracks in Semiconductor Standard Cells
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Solution Overview
Problem
Current methods for defining routing tracks in standard cell semiconductor devices are limited in reducing the size of standard cells, as the separation between features approaches the wavelength of light used in photolithographic methods, necessitating improved techniques for further miniaturization.
Innovation Solution
A method involving the formation of multiple mandrels above a target layer, with spacers on their sidewalls, followed by transferring these spacers into a dummy layer to create dummy features that define off-center routing tracks, and subsequently forming a second set of spacers to fill gaps and define a central routing track, allowing for non-uniform pitch and reduced height of the standard cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple patterning is used to reduce feature separation below wavelength limits, then feature density is enhanced, but standard cell size reduction is still insufficient
Solution Approach 1:
The routing track definition process is segmented into multiple independent spacer formation steps. First spacers are formed on mandrels, then mandrels are removed, and second spacers are formed on the first spacers. This segmentation allows each step to be optimized independently, achieving better overall density than conventional single-step patterning.
Solution Approach 2:
The patent transitions from planar patterning to three-dimensional spacer-based patterning. By forming spacers on the sidewalls of mandrels and then using those spacers as new mandrels for second spacers, the method exploits the vertical dimension to achieve higher feature density and more precise routing track definition.
2Ease of manufacture
If uniform pitch routing tracks are used, then manufacturing simplicity is maintained, but standard cell height cannot be minimized
Solution Approach 1:
The patent applies different spacing configurations to different regions of the standard cell. Central routing tracks have different pitch than off-center routing tracks, with each region optimized for its specific function. This local optimization allows minimum height to be achieved while maintaining manufacturability through the systematic spacer formation process.
Solution Approach 2:
The first spacers are formed as preliminary structures that define the positions of off-center routing tracks. These first spacers then serve as the basis for forming the second spacers that define the central routing tracks. This preliminary action enables the complex non-uniform pitch pattern to be achieved through a systematic, controllable process.
3Manufacturing precision
If feature separation approaches photolithographic wavelength, then conventional single patterning becomes insufficient, but multi-patterning increases process complexity
Solution Approach 1:
The first spacers automatically serve as the mandrels for forming the second spacers. The material deposited to form the second spacers uses the first spacers as self-aligned templates, eliminating the need for separate lithographic alignment steps and reducing process complexity while maintaining high precision.
Solution Approach 2:
The patent changes the critical dimension control parameter from lithographic wavelength to spacer thickness. By controlling the deposition thickness of the spacer materials, the routing track dimensions are defined with precision independent of photolithographic wavelength limitations, achieving high manufacturing precision without conventional multi-patterning complexity.
Data Source
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AI summary
Methods for defining routing tracks in a target layer (100) above a standard cell semiconductor device (1) comprising a device layer (10) and routing tracks for contacting the device layer are disclosed, wherein mandrels (111, 112, 113) and a first and a second set of spacers (121, 122, 123, 124; 140) are used for defining the routing tracks. The routing tracks include at least two pairs of off-centre routing tracks (T1, T2; T3, T4), a central routing track (T5) arranged between the pairs of off-centre routing tracks, and at least two edge tracks (T6, T7) arranged on opposing sides of the at least two pairs of off-centre routing tracks, wherein a minimum distance (W3, W4) between an off-centre routing track and the central routing track next to the off-centre routing track, is smaller than a minimum distance (W2, W5) between adjacent off-centre routing tracks.