Element Chip Singulation with Resin Reflow for Smooth Sidewalls
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Solution Overview
Problem
Conventional element chip manufacturing methods using plasma etching often result in rough side surfaces and edge protrusions of the wiring layer, leading to potential separation issues during the Bosch process.
Innovation Solution
A method involving a substrate preparation, resin layer formation, laser-induced opening creation, reflow process to reduce the opening, and plasma etching for singulation, where the resin layer acts as a mask to prevent wiring layer separation and smooth side surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If plasma etching is performed along the dividing area to obtain element chips, then singulation is achieved, but the side surfaces become rough and wiring layer edge portions protrude
Solution Approach 1:
The patent applies preliminary action by forming a resin layer covering the wiring layer before plasma etching, and creating openings in the resin layer at the dividing area prior to etching. This preliminary preparation ensures that during subsequent plasma etching, the resin layer acts as a mask to prevent wiring layer damage and the pre-formed openings guide precise etching along the dividing area, thereby avoiding side surface roughness and wiring layer edge protrusions while maintaining high singulation efficiency
2Productivity
If Bosch process is applied in etching to improve etching speed, then productivity increases, but wiring layer separation occurs due to edge protrusions
Solution Approach 1:
The patent introduces the resin layer as an intermediary between the plasma etching process and the wiring layer. This resin layer mask absorbs the harsh effects of high-speed Bosch process etching, preventing direct plasma exposure to the wiring layer edges. The pre-formed openings in the resin layer guide the etching precisely along the dividing area, ensuring that even at high etching speeds, the wiring layer remains protected and properly aligned, thus maintaining wiring layer integrity while achieving high productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively suppresses wiring layer separation and reduces side surface roughness, improving the quality and integrity of the element chips produced.
Implementation Method 1
an opening formation step of irradiating the resin layer and the wiring layer in the dividing area with a laser beam from the first principal surface side to form an opening in which the semiconductor layer is exposed
Implementation Method 2
a reflow step of reducing the opening by reflowing the resin layer
Implementation Method 3
a singulation step of dividing the substrate into a plurality of element chips each including a different one of the element areas, by performing etching of the substrate with plasma along the opening reduced in the reflow step
Data Source
AI summary
An element chip manufacturing method disclosed herein includes a preparation process of preparing a substrate having a semiconductor layer, a wiring layer, a plurality of element areas and a dividing area, a resin layer formation process of forming a resin layer covering the wiring layer, an opening formation process of irradiating the wiring layer and the resin layer in the dividing area to form an opening in which the semiconductor layer is exposed in the dividing area, a reflow process of reducing the opening by reflowing the resin layer, and a singulation process of dividing the substrate into a plurality of element chips each including a different one of the element areas, by performing etching of the substrate with plasma along the opening reduced in the reflow process, using the resin layer as a mask.