Bottom Dielectric Isolator Layout for CFET Leakage Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing stacked device structures, such as complementary field-effect transistors (CFET), due to current leakage issues, which are exacerbated by the increasing complexity and density of integrated circuits.
Innovation Solution
The implementation of a bottom dielectric isolator under source/drain epitaxial structures and a gate structure of a bottom nanostructure FET to prevent current leakage, utilizing a method that includes forming a fin structure over a bottom dielectric isolator, growing source/drain epitaxial structures, and replacing a dummy gate with a gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked device structures (CFET) are implemented to increase device density, then functional density is improved, but current leakage occurs between source/drain epitaxial structures and gate structure
Solution Approach 1:
A bottom dielectric isolator is introduced as an intermediary layer between the source/drain epitaxial structures and the gate structure. This dielectric isolator acts as a mediator that prevents direct electrical contact and current leakage while allowing the stacked CFET structure to maintain high device density. The dielectric material provides electrical isolation without compromising the functional integration of the stacked devices.
2Productivity
If geometry size is decreased to increase device density, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The bottom dielectric isolator is formed in advance during the fabrication process, before the gate structure and source/drain epitaxial structures are fully assembled. This preliminary action ensures that the isolation layer is already in place to prevent current leakage, allowing subsequent processing steps to proceed with smaller geometry sizes without compromising manufacturing precision. The pre-formed isolator provides a stable foundation for high-density stacking.
3Quantity of substance
If complexity of processing is increased to achieve higher device density, then functional density is improved, but reliability deteriorates due to current leakage
Solution Approach 1:
The bottom dielectric isolator serves as a critical intermediary element that resolves the reliability issue in complex stacked structures. By placing this isolator at the interface between source/drain epitaxial structures and the gate structure, the patent eliminates current leakage pathways that would otherwise compromise device reliability, enabling the complex CFET architecture to function reliably at high density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents current leakage between source/drain epitaxial structures and the gate structure, enhancing the performance and reliability of CFET devices by maintaining high device density and complexity.
Implementation Method 1
a bottom dielectric isolator under source/drain epitaxial structures and a gate structure of a bottom nanostructure FET to prevent current leakage
Data Source
AI summary
A method includes forming a fin structure over a bottom dielectric isolator and a substrate. The fin structure includes a bottom channel layer, a sacrificial layer over the bottom channel layer, and a top channel layer over the sacrificial layer. A dummy gate is formed across the fin structure. Portions of the fin structure not covered by the gate structure are removed to expose a top surface of the bottom dielectric isolator. First source/drain epitaxial structures are epitaxially grown over the bottom dielectric isolator and are connected to the bottom channel layer. Second source/drain epitaxial structures are epitaxially grown over the first source/drain epitaxial structures and are connected to the top channel layer. The dummy gate and the sacrificial layer are replaced with a gate structure.