3D Memory Gate Stack Layout for Stable Gate Contact Alignment
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Solution Overview
Problem
Current semiconductor devices face challenges in maximizing memory cells and ensuring stable connections due to misalignment and deviation issues in gate contact portions, which affect data storage capacity and reliability.
Innovation Solution
The semiconductor device incorporates a gate stacking structure with a bottom gate electrode adjacent to a channel structure and a distinct bottom insulating portion, ensuring proper insulation and alignment, and a manufacturing method involving sacrificial layers and insulating materials to form channel and gate contact structures, enhancing the connection stability and data storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate contact portions are formed to connect to gate electrodes, then electrical connection is achieved, but misalignment and deviation occur affecting reliability
Solution Approach 1:
The patent introduces an insulating pattern as an intermediary element positioned between the gate contact portion and remaining gate electrodes. This insulating pattern serves as a mediator that provides both electrical insulation and precise positional reference, enabling accurate alignment of the gate contact portion with the connection gate electrode while preventing electrical interference with adjacent gate electrodes, thus resolving the misalignment and reliability issues
Solution Approach 2:
The insulating pattern is formed in advance before the gate contact portion is created. By pre-establishing the insulating pattern with the correct position and dimensions, the subsequent formation of the gate contact portion can be precisely guided to align with the connection gate electrode, preventing misalignment and deviation issues that would otherwise affect connection stability
2Quantity of substance
If three-dimensionally arranged memory cells are implemented, then data storage capacity increases, but device complexity increases
Solution Approach 1:
The patent implements memory cells arranged in three dimensions by stacking multiple gate electrodes vertically to form a gate stacking structure. This dimensional transition from planar to vertical arrangement allows significantly more memory cells to be packed into the same footprint area, increasing data storage capacity while managing complexity through systematic layering and the use of insulating patterns for organization and insulation
3Reliability
If insulating distance is increased to prevent electrical interference, then reliability improves, but area occupied increases
Solution Approach 1:
The insulating pattern is applied locally only where needed - specifically between the gate contact portion and remaining gate electrodes - rather than uniformly across the entire device. This localized insulation approach provides necessary electrical isolation to prevent interference and improve reliability, while minimizing the additional area occupied by insulation structures, thus efficiently balancing reliability requirements with area constraints
Data Source
AI summary
A semiconductor device includes a cell area, wherein the cell area includes: a cell array area; a connection area; a gate stacking structure including a plurality of gate electrodes, wherein the gate stacking structure includes an upper structure and a lower structure; a plurality of channel structures that penetrates the gate stacking structure in the cell array area; and a plurality of gate contact portions that penetrates the gate stacking structure in the connection area, wherein a bottom gate electrode in the cell array area is in a bottom portion of the upper structure and is adjacent to a channel structure among the plurality of channel structures, and wherein a bottom insulating portion in the connection area is in the bottom portion of the upper structure and is adjacent to a gate contact portion among the plurality of gate contact portions.