3D Memory Structure With Carrier Injection for Wider Memory Window
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Solution Overview
Problem
Existing 3D NAND-type memory technologies face challenges in high-speed read/write access and reliability due to difficulties in erasing and programming operations, particularly with ferroelectric FETs, which result in reduced memory window (MW) and potential gate breakdown.
Innovation Solution
The formation of doped regions in the substrate to create NPN or PNP junctions, which inject charge carriers into the channel layer, forming an inversion layer that screens electric fields and concentrates them in the ferroelectric layer, thereby improving erasing and programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ferroelectric FETs are used in 3D NAND memory, then storage capacity and integration density are improved, but erasing and programming operations become difficult resulting in reduced memory window and potential gate breakdown
Solution Approach 1:
A charge trap layer is introduced as an intermediary between the ferroelectric layer and the channel. This charge trap layer captures excess charge carriers generated during erasing and programming operations, preventing them from reaching and damaging the gate. The charge trap layer thus mediates the interaction between the ferroelectric layer and channel, enabling reliable operation while maintaining the benefits of ferroelectric memory.
Solution Approach 2:
The charge trap layer is pre-formed in the substrate before stacking the ferroelectric layers. This preliminary action prepares the structure to handle charge carriers that will be generated during subsequent programming and erasing operations, preventing gate breakdown before it can occur.
2Quantity of substance
If ferroelectric FETs are used, then memory integration density is improved, but erasing and programming efficiency deteriorates resulting in small memory window
Solution Approach 1:
The charge trap layer serves as a mediator that facilitates efficient charge carrier management. By capturing and holding charge carriers, it enables complete erasing of the ferroelectric layer, achieving a clear distinction between programmed and erased states, thus improving memory window and operation efficiency.
Solution Approach 2:
The invention changes the electrical parameters of the system by introducing a layer with different charge trapping characteristics. This modifies the charge distribution and electric field profiles during programming and erasing operations, improving the memory window and operational efficiency.
3Quantity of substance
If 3D memory array architecture is implemented, then storage capacity is improved, but read/write access speed deteriorates
Solution Approach 1:
The charge trap layer is pre-formed to rapidly capture charge carriers during programming and erasing operations. This preliminary charge capture mechanism accelerates the programming and erasing speeds, mitigating the speed penalty associated with 3D memory architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency of erasing and programming operations, mitigates the small MW issue, and improves the reliability of the memory structure by reducing the risk of gate breakdown.
Implementation Method 1
The doped regions are doped with dopants of a second conductivity type complementary to the dopants of the first conductivity type in the substrate, and form NPN or PNP junctions with the substrate
Implementation Method 2
inject carriers into the channel layer, and thus an inversion layer that is able to help to screen electric fields toward the channel layer may be formed
Implementation Method 3
an inversion layer that is able to help to screen electric fields toward the channel layer may be formed. Therefore, the electric fields generated to flip dipoles can be concentrated in the ferroelectric layer
Data Source
AI summary
A method for forming a semiconductor memory structure includes following operations. A plurality of doped regions are formed in a semiconductor substrate. The doped regions are separated from each other. A stack including a plurality of first insulating layers and a plurality of second insulating layers alternately arranged is formed over the semiconductor substrate. A first trench is formed in the stack. The second insulating layers are replaced with a plurality of conductive layers. A second trench is formed. A charge-trapping layer and a channel layer are formed in the second trench. An isolation structure is formed to fill the second trench. A source structure and a drain structure are formed at two sides of the isolation structure.